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| HT45RM03 Brushless DC Motor Type 8-Bit OTP MCU Technical Document * Tools Information * FAQs * Application Note Features * Operating voltage: * Up to 0.33ms instruction cycle with 12MHz system fSYS=4MHz: 2.2V~5.5V fSYS=8MHz: 3.3V~5.5V fSYS=12MHz: 4.5V~5.5V * 23 bidirectional I/O lines (max.) * 4 interrupt input shared with 4 I/O line * Two 8-bit programmable timer/event counter with clock at VDD=5V * 8-level subroutine nesting * 8 channels 9-bit resolution A/D converter * 3-channel 10-bit PWM with complementary output shared with six I/O lines * Bit manipulation instruction * 15-bit table read instruction * 63 powerful instructions * All instructions in one or two machine cycles * Low voltage reset function * One operational Amplifier * One Comparator with interrupt function * 28-pin SKDIP/SOP packages overflow interrupt and 7-stage prescaler * On-chip crystal and RC oscillator * Watchdog Timer * 409615 program memory * 1928 data memory RAM * Supports PFD for sound generation * HALT function and wake-up feature reduce power consumption General Description The HT45RM03 is 8-bit, high performance, RISC architecture microcontroller devices specifically designed for A/D applications that interface directly to analog signals, such as those from sensors. The advantages of low power consumption, I/O flexibility, programmable frequency divider, timer functions, oscillator options, multi-channel A/D Converter, Pulse Width Modulation function, HALT and wake-up functions, enhance the versatility of these devices to suit a wide range of A/D application possibilities such as sensor signal processing, motor driving, industrial control, consumer products, subsystem controllers, etc. Rev. 1.00 1 January 11, 2007 HT45RM03 Block Diagram PA PA PA PA 4 /IN 5 /IN 6 /IN 7 /IN T0A T0B T0C T1 TM R0C TM R0 PFD0 M U P r e s c a le r X fS YS P B 7 /A N 7 /T M R 0 /T M R 1 In te rru p t C ir c u it STACK P ro g ra m ROM P ro g ra m C o u n te r IN T C TM R1C TM R1 PFD1 fS In s tr u c tio n R e g is te r M U X W DT P r e s c a le r PDC PD 8 -C h a n n e l A /D C o n v e rte r PBC ALU T im in g G e n e ra to r S h ifte r PA3,PA5 STATUS PB OPA P o rt B WDT M U X RC OSC YS M U P r e s c a le r X fS YS P B 7 /A N 7 /T M R 0 /T M R 1 /4 MP D a ta M e m o ry P o rt D P D 0 /P F D In s tr u c tio n D ecoder MUX PB PB PB PB PB PA PA PA PA PA PA PA PA PC PC PC PC PC PC 0 /A 2 /A 3 /A 4 /A 7 /A 0 /O 1 /C 2 /C 3 /C 4 /IN 5 /IN 6 /IN 7 /IN 0 /P 1 /P 2 /P 3 /P 4 /P 5 /P N0 N2 N3 N4 N7 PV V IN V IN OU T0 T0 T0 T1 WM WM WM WM WM WM ~ /O /O ~ /T PB P P PB M 1 /A N 1 OUT V IN N 6 /A N 6 R 0 /T M R 1 PAC OSC2 OS RE VD VS S S D C1 ACC LVR PA C o m p a ra to r PC PCC PW M P o rt A IN P P N T A B C 0 0 1 1 2 2 P o rt C Pin Assignment P B 5 /A N 5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 P B 4 /A N 4 P A 3 /C O U T P A 2 /C V IN N P A 1 /C V IN P P A 0 /O P V IN P P B 3 /A N 3 /O P V IN N P B 2 /A N 2 /O P O U T P B 1 /A N 1 P B 0 /A N 0 VSS P C 0 /P W M 0 P C 1 /P W M 0 P C 2 /P W M 1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 P B 6 /A N 6 P B 7 /A N 7 /T M R 0 /T M R 1 P A 4 /IN T 0 A P A 5 /IN T 0 B P A 6 /IN T 0 C P A 7 /IN T 1 OSC2 OSC1 VDD RES P D 0 /P F D P C 5 /P W M 2 P C 4 /P W M 2 P C 3 /P W M 1 H T45R M 03 2 8 S K D IP -A /S O P -A Rev. 1.00 2 January 11, 2007 HT45RM03 Pad Description Pad Name I/O Option Description Bidirectional 8-bit input/output port. Each bit can be configured as wake-up input by ROM code option. Software instructions determine the CMOS output or Schmitt trigger input with or without pull-high resistor (determined by pull-high options: bit option). The INT0A, INT0B, INT0C and INT1 are pin-shared with PA4~PA7. The CVINP, CVINN and COUT are pin-shared with PA1, PA2 and PA3. Once the Comparator function is used, the internal registers related to PA1, PA2 cannot be used, PA3 can be used as input only, and the PA1, PA2 I/O function and pull-high resistor are disabled automatically. Software instructions determine the Comparator function to be used. The OPVINP is pin-shared with PA0. Bidirectional 8-bit input/output port. Software instructions determine the output, Schmitt trigger input with or without pull-high resistor (determined by pull-high option: bit option) or A/D input. Once a PB line is selected as an A/D input (by using software control), the I/O function and pull-high resistor are disabled automatically. The OPVINP, OPVINN and OPOUT are pin-shared with PA0, PB3/AN3 and PB2/AN2 respectively. Once the OPA function is used, the internal registers related to PA0, PB3 and PB2 cannot be used, and the I/O function and pull-high resistor are disabled automatically. Software instructions determine the OPA function to be used. Bidirectional 6-bit input/output port. Software instructions determine the CMOS output, Schmitt trigger input with or without a pull-high resistor (determined by pull-high option: byte option). The PWM0~PWM2 and PWM0~PWM2 output function are pin-shared with PC0, PC2, PC4 and PC1, PC3, PC5 respectively by software control. Bidirectional 1-bit input/output port. Software instructions determine the CMOS output, Schmitt trigger input with or without a pull-high resistor (determined by pull-high option: bit option). The PFD output function is pin-shared with PD0. Schmitt trigger reset input. Active low. Positive power supply Negative power supply, ground. OSC1, OSC2 are connected to an RC network or a Crystal (determined by options) for the internal system clock. In the case of RC operation, OSC2 is the output terminal for 1/4 system clock. PA0/OPVINP PA1/CVINP PA2/CVINN PA3/COUT PA4/INT0A PA5/INT0B PA6/INT0C PA7/INT1 I/O Wake-up Pull-high PB0/AN0 PB1/AN1 PB2/AN2/OPOUT I/O PB3/AN3/OPVINN PB4/AN4~PB6/AN6 PB7/AN7/TMR0/TMR1 Pull-high PC0/PWM0 PC1/PWM0 PC2/PWM1 PC3/PWM1 PC4/PWM2 PC5/PWM2 I/O Pull-high PD0/PFD I/O Pull-high PFD 3/4 3/4 3/4 Crystal or RC RES VDD VSS OSC1 OSC2 I 3/4 3/4 I O Absolute Maximum Ratings Supply Voltage ...........................VSS-0.3V to VSS+6.0V Input Voltage..............................VSS-0.3V to VDD+0.3V IOL Total ..............................................................150mA Total Power Dissipation .....................................500mW Storage Temperature ............................-50C to 125C Operating Temperature...........................-40C to 85C IOH Total............................................................-100mA Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Rev. 1.00 3 January 11, 2007 HT45RM03 D.C. Characteristics Test Conditions Symbol Parameter VDD 3/4 VDD Operating Voltage 3/4 3/4 IDD1 Operating Current (Crystal OSC, RC OSC) Operating Current (Crystal OSC, RC OSC) Operating Current (Crystal OSC, RC OSC) Standby Current (WDT Enabled) Standby Current (WDT Disabled) Input Low Voltage for I/O Ports, TMR0, TMR1, INT0A, INT0B, INT0C and INT1 Input High Voltage for I/O Ports, TMR0, TMR1, INT0A, INT0B, INT0C and INT1 Input Low Voltage (RES) Input High Voltage (RES) Low Voltage Reset 1 Low Voltage Reset 2 Low Voltage Reset 3 3V 5V 3V 5V 5V 3V No load, system HALT 5V 3V No load, system HALT 5V 3/4 3/4 Conditions fSYS=4MHz fSYS=8MHz fSYS=12MHz No load, fSYS=4MHz ADC disable No load, fSYS=8MHz ADC disable No load, fSYS=12MHz ADC disable 2.2 3.3 4.5 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0 3/4 3/4 3/4 1 2.5 2 4 5 3/4 3/4 3/4 3/4 3/4 5.5 5.5 5.5 2 5 4 8 10 5 10 1 2 0.3VDD V V V mA mA mA mA mA mA mA mA mA V Min. Typ. Max. Unit Ta=25C IDD2 IDD3 ISTB1 ISTB2 VIL1 VIH1 VIL2 VIH2 VLVR1 VLVR2 VLVR3 3/4 3/4 3/4 3/4 3/4 3/4 3V 3/4 3/4 3/4 Configuration option: 4.2V Configuration option: 3.15V Configuration option: 2.1V VOL=0.1VDD VOL=0.1VDD VOH=0.9VDD VOH=0.9VDD 3/4 3/4 3/4 3/4 3/4 0.7VDD 0 0.9VDD 3.98 2.98 1.98 4 10 -2 -5 20 10 0 3/4 3/4 3/4 3/4 3/4 3/4 4.2 3.15 2.1 8 20 -4 -10 60 30 3/4 0.5 0.5 1.5 VDD 0.4VDD VDD 4.42 3.32 2.22 3/4 3/4 3/4 3/4 100 50 VDD 1 1 3 V V V V V V mA mA mA mA kW kW V LSB mA mA IOL I/O Port Sink Current 5V 3V I/O Port Source Current 5V 3V Pull-high Resistance 5V A/D Input Voltage A/D Conversion Error Additional Power Consumption if A/D Converter is Used 3/4 3/4 3V 5V IOH RPH VAD EAD IADC Rev. 1.00 4 January 11, 2007 HT45RM03 A.C. Characteristics Symbol Parameter Test Conditions VDD 3/4 fSYS System Clock 3/4 3/4 fTIMER Timer I/P Frequency (TMR0/TMR1) 3/4 3V 5V 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Conditions 2.2V~5.5V 3.3V~5.5V 4.5V~5.5V 3/4 3/4 3/4 3/4 Wake-up from HALT 3/4 3/4 3/4 3/4 3/4 Min. 400 400 400 0 45 32 1 3/4 1 1 3/4 3/4 0.25 Typ. 3/4 3/4 3/4 3/4 90 65 3/4 1024 3/4 3/4 72 32 1 Max. 4000 8000 12000 4000 180 130 3/4 3/4 3/4 3/4 3/4 3/4 2 Ta=25C Unit kHz kHz kHz kHz ms ms ms *tSYS ms ms tAD tAD ms tWDTOSC Watchdog Oscillator Period tRES tSST tINT tAD tADC tADCS tLVR External Reset Low Pulse Width System Start-up Timer Period Interrupt Pulse Width A/D Clock Period A/D Conversion Time A/D Sampling Time Low Voltage Width to Reset Note: *tSYS=1/fSYS OP Amplifier Electrical Characteristics Symbol Parameter Test Conditions VDD 3/4 5V 3/4 3/4 3/4 Conditions 3/4 By calibration 3/4 3/4 VDD=5V VCM=0~VDD-1.4V 3/4 No load RL=1MW, CL=100pF Min. Typ. Max. Ta=25C Unit D.C. Electrical Characteristic VDD VOS VCM PSRR CMRR Operating Voltage Input Offset Voltage Common Mode Voltage Range Power Supply Rejection Ratio Common Mode Rejection Ratio 3 -2 VSS 60 60 3/4 3/4 3/4 3/4 3/4 5.5 +2 VDD-1.4 3/4 3/4 V mV V dB dB A.C. Electrical Characteristic AOL SR GBW Open Loop Gain Slew Rate+, RateGain Band Width 3/4 3/4 3/4 60 3/4 3/4 80 1 3/4 3/4 3/4 100 dB V/ms kHz Comparator Electrical Characteristics Symbol VDD VOS VCM tPD Parameter Operating Voltage Comparator Input Offset Voltage Comparator Common Mode Voltage Range Comparator Response Time Test Conditions VDD 3/4 5V 3/4 3/4 Conditions 3/4 By calibration 3/4 3/4 Min. 3 -2 0 3/4 Typ. 3/4 3/4 3/4 3/4 Max. 5.5 2 VDD-1.4 2 Ta=25C Unit V mV V ms Rev. 1.00 5 January 11, 2007 HT45RM03 Functional Description Execution Flow The system clock for the microcontroller is derived from either a crystal or an RC oscillator. The system clock is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to effectively execute in a cycle. If an instruction changes the program counter, two cycles are required to complete the instruction. Program Counter - PC The program counter (PC) controls the sequence in which the instructions stored in program PROM are executed and its contents specify full range of program memory. After accessing a program memory word to fetch an inS y s te m C lo c k T1 T2 T3 T4 T1 struction code, the contents of the program counter are incremented by one. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise proceed with the next instruction. The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination will be within 256 locations. When a control transfer takes place, an additional dummy cycle is required. T2 T3 T4 T1 T2 T3 T4 O S C 2 ( R C o n ly ) PC PC PC+1 PC+2 F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 ) F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C ) F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 ) Execution Flow Program Counter *11 0 0 0 0 0 0 0 *11 #11 S11 *10 0 0 0 0 0 0 0 *10 #10 S10 *9 0 0 0 0 0 0 0 *9 #9 S9 *8 0 0 0 0 0 0 0 *8 #8 S8 *7 0 0 0 0 0 0 0 @7 #7 S7 *6 0 0 0 0 0 0 0 @6 #6 S6 *5 0 0 0 0 0 0 0 @5 #5 S5 *4 0 0 0 0 1 1 1 @4 #4 S4 *3 0 0 1 1 0 0 1 @3 #3 S3 *2 0 1 0 1 0 1 0 @2 #2 S2 *1 0 0 0 0 0 0 0 @1 #1 S1 *0 0 0 0 0 0 0 0 @0 #0 S0 Mode Initial Reset Comparator Interrupt External Interrupt 0 External Interrupt 1 PWM Period Interrupt Timer/Event Counter 0 Overflow Timer/Event Counter 1 Overflow Skip Loading PCL Jump, Call Branch Return from Subroutine Program Counter + 2 Program Counter Note: *11~*0: Program counter bits #11~#0: Instruction code bits S11~S0: Stack register bits @7~@0: PCL bits Rev. 1.00 6 January 11, 2007 HT45RM03 Program Memory - ROM The program memory is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 409615 bits, addressed by the program counter and table pointer. Certain locations in the program memory are reserved for special usage: * Location 000H 000H 004H 008H 00C H 010H 014H 018H D e v ic e In itia liz a tio n P r o g r a m C o m p a ra to r In te rru p t E x te rn a l In te rru p t 0 E x te rn a l In te rru p t 1 PW M P e r io d In te r r u p t P ro g ra m M e m o ry T im e r /E v e n t C o u n te r 0 O v e r flo w T im e r /E v e n t C o u n te r 1 O v e r flo w These area is reserved for program initialization. After chip reset, the program always begins execution at location 000H. * Location 004H n00H nFFH L o o k - u p T a b le ( 2 5 6 w o r d s ) These area is reserved for the Comparator interrupt service program. If the Comparator output pin is activated, and if the interrupt is enable and the stack is not full, the program begins execution at location 004H. * Location 008H FFFH L o o k - u p T a b le ( 2 5 6 w o r d s ) 1 5 b its N o te : n ra n g e s fro m 0 to F These area is reserved for the external interrupt 0 service program. If the INT0A, INT0B or INT0C input pin is activated, the interrupt is enabled and the stack is not full, the program begins execution at location 008H. * Location 00CH Program Memory * Table location These area is reserved for the external interrupt 1 service program. If the INT1 input pin is activated, the interrupt is enabled and the stack is not full, the program begins execution at location 00CH. * Location 010H These area is reserved for the PWM period interrupt service program. If a PWM period interrupt results from a PWM counter overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 010H. * Location 014H These area is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt results from a Timer/Event Counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 014H. * Location 018H These area is reserved for the Timer/Event Counter 1 interrupt service program. If a timer interrupt results from a Timer/Event Counter 1 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 018H. Any location in the PROM space can be used as look-up tables. The instructions TABRDC [m] (the current page, 1 page=256 words) and TABRDL [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are transferred to the lower portion of TBLH, and the remaining 1 bit is read as 0. The Table Higher-order byte register (TBLH) is read only. The table pointer (TBLP) is a read/write register (07H), which indicates the table location. Before accessing the table, the location must be placed in TBLP. The TBLH is read only and cannot be restored. If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR. Errors can occur. In other words, using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read instruction has to be applied in both the main routine and the ISR, the interrupt is supposed to be disabled prior to the table read instruction. It will not be enabled until the TBLH has been backed up. All table related instructions require two cycles to complete the operation. These areas may function as normal program memory depending upon the requirements. Table Location Instruction TABRDC [m] TABRDL [m] *11 P11 1 *10 P10 1 *9 P9 1 *8 P8 1 *7 @7 @7 *6 @6 @6 *5 @5 @5 *4 @4 @4 *3 @3 @3 *2 @2 @2 *1 @1 @1 *0 @0 @0 Table Location Note: *11~*0: Table location bits @7~@0: Table pointer bits 7 P11~P8: Current program counter bits Rev. 1.00 January 11, 2007 HT45RM03 Stack Register - STACK This is a special part of the memory which is used to save the contents of the Program Counter only. The stack is organized into 8 levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the stack pointer (SP) and is neither readable nor writeable. At a subroutine call or interrupt acknowledgment, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledgment will be inhibited. When the stack pointer is decremented (by RET or RETI), the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. In a similar case, if the stack is full and a CALL is subsequently executed, stack overflow occurs and the first entry will be lost (only the most recent 8 return addresses are stored). Data Memory - RAM The data memory is designed with 2268 bits. The data memory is divided into two functional groups: special function registers and general purpose data memory (1928). Most are read/write, but some are read only. The special function registers include the indirect addressing registers (00H;02H), Timer/Event Counter 0 (TMR0;0DH), Timer/Event Counter 0 control register (TMR0C;0EH), Timer/Event Counter 1 (TMR1:10H), Timer/Event Counter 1 control register (TMR1C; 11H), program counter lower-order byte register (PCL;06H), memory pointer registers (MP0;01H, MP1;03H), accumulator (ACC;05H), table pointer (TBLP;07H), table higher-order byte register (TBLH;08H), status register (STATUS;0AH), interrupt control register 0 (INTC0; 0BH), PWM higher-order byte register (PWMH;1AH), PWM lower-order byte register (PWML;1BH), PWM Control register (PWMC;1CH), Miscellaneous register (MISC;1DH), the A/D result lower-order byte register (ADRL;20H), the A/D result higher-order byte register (ADRH;21H), the A/D control register (ADCR;22H), the A/D clock setting register (ACSR;23H), the Comparator Control register (CMPC;24H), the Operational Amplifier Control register (OPAC;25H), I/O registers (PA;12H, PB;14H, PC;16H, PD;18H) and I/O control registers (PAC;13H, PBC;15H, PCC;17H, PDC;19H). The remaining space before the 26H or 40H is reserved for future expanded usage and reading these locations will get 00H. The general purpose data memory, addressed from 40H to FFH, is used for data and control information under instruction commands. 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H ADRH ADRL ADCR ACSR CMPC OPAC TM R1 TM R1C PA PAC PB PBC PC PCC PD PDC PW MH PW ML PW MC M IS C IN T C 1 S p e c ia l P u r p o s e D a ta M e m o ry TM R0 TM R0C ACC PCL TBLP TBLH W DTS STATUS IN T C 0 In d ir e c t A d d r e s s in g R e g is te r 0 MP0 In d ir e c t A d d r e s s in g R e g is te r 1 MP1 3FH 40H FFH G e n e ra l P u rp o s e D a ta M e m o ry (1 9 2 B y te s ) :U nused R e a d a s "0 0 " RAM Mapping All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by SET [m].i and CLR [m].i. They are also indirectly accessible through memory pointer registers (MP0;01H/MP1;03H). Rev. 1.00 8 January 11, 2007 HT45RM03 Indirect Addressing Register The method of indirect addressing allows data manipulation using memory pointers instead of the usual direct memory addressing method where the actual memory address is defined. Any action on the indirect addressing registers will result in corresponding read/write operations to the memory location specified by the corresponding memory pointers. This device contains two indirect addressing registers known as IAR0 and IAR1 and two memory pointers MP0 and MP1. Note that these indirect addressing registers are not physically implemented and that reading the indirect addressing registers indirectly will return a result of 00H and writing to the registers indirectly will result in no operation. The two memory pointers, MP0 and MP1, are physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. When any operation to the relevant indirect addressing registers is carried out, the actual address that the microcontroller is directed to is the address specified by the related memory pointer. Direct data transfer between two indirect addressing registers is not supported. The memory pointer registers, MP0 and MP1, are both 8-bit registers used to access the Program Memory by combining corresponding indirect addressing registers. Accumulator The accumulator is closely related to ALU operations. It is also mapped to location 05H of the data memory and can carry out immediate data operations. The data movement between two data memory locations must pass through the accumulator. Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions: * Arithmetic operations (ADD, ADC, SUB, SBC, DAA) * Logic operations (AND, OR, XOR, CPL) * Rotation (RL, RR, RLC, RRC) * Increment and Decrement (INC, DEC) * Branch decision (SZ, SNZ, SIZ, SDZ ....) The ALU not only saves the results of a data operation but also changes the status register. Status Register - STATUS This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). It also records the status information and controls the operation sequence. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition operations related to the status register may give different results from those intended. The TO flag can be affected only by system power-up, a WDT time-out or executing the CLR WDT or HALT instruction. The PDF flag can be affected only by executing the HALT or CLR WDT instruction or a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status are important and if the subroutine can corrupt the status register, precautions must be taken to save it properly. Function Bit No. 0 Label C C is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared. OV is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PDF is cleared by system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction. TO is cleared by system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0 Status (0AH) Register 1 2 3 4 5 6~7 AC Z OV PDF TO 3/4 Rev. 1.00 9 January 11, 2007 HT45RM03 Interrupt The devices provides four external interrupts, two internal Timer/Event Counter 0/1 interrupts, one comparator interrupt, and PWM period interrupt. The interrupt control register 0 (INTC0;0BH) and interrupt control register 1 (INTC1;1EH) both contain the interrupt control bits that are used to set the enable/disable status and interrupt request flags. Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may happen during this interval but only the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the EMI bit and the corresponding bit of INTC0 and INTC1 may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be prevented from becoming full. All these kinds of interrupts have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at specified location in the program memory. Only the program counter is pushed onto the stack. If the contents of the register or status register (STATUS) are altered by the interrupt service program which corrupts the desired control sequence, the contents should be saved in advance. The Comparator output Interrupt is initialized by setting the Comparator 0 output Interrupt request flag (CF; bit 4 of the INTC0), which is caused by a falling edge transition of comparator output. After the interrupt is enabled, and the stack is not full, and the CF bit is set, a subrouBit No. 0 1 2 3 4 5 6 7 Label EMI ECI EEI0 EEI1 CF EI0F EI1F 3/4 tine call to location 04H occurs. The related interrupt request flag (CF) is reset, and the EMI bit is cleared to disable further maskable interrupts. External interrupts are triggered by a an edge transition of INT0A, INT0B, INT0C or INT1 (software control: high to low, low to high, low to high or high to low), and the related interrupt request flag (EIF0; bit 5 of INTC0, EIF1; bit 6 of INTC0) is set as well. After the interrupt is enabled, the stack is not full, and the external interrupt is active, a subroutine call to location 08H or 0CH occurs. The interrupt request flag (EIF0 or EIF1) and EMI bits are all cleared to disable other maskable interrupts. The PWM period interrupt is initialized by setting the PWM period interrupt request flag (PWMF; bit 4 of INTC1), that is caused by a regular PWM period signal. After the interrupt is enabled, and the stack is not full, and the PWMF bit is set, a subroutine call to location 10H occurs. The related interrupt request flag (PWMF) is reset and the EMI bit is cleared to disable further maskable interrupts. The internal Timer/Event Counter 0 interrupt is initialized by setting the Timer/Event Counter 0 interrupt request flag (T0F; bit 5 of the INTC1), which is normally caused by a timer overflow. After the interrupt is enabled, and the stack is not full, and the T0F bit is set, a subroutine call to location 014H occurs. The related interrupt request flag (T0F) is reset, and the EMI bit is cleared to disable further interrupts. The Timer/Event Counter 1 is operated in the same manner, The Timer/Event Counter 1 related interrupt request flag is T1F (bit 6 of the INTC1) and its subroutine call location is 018H. The related interrupt request flag (T1F) will be reset and the EMI bit cleared to disable further interrupts. Function Control the master (global) interrupt (1=enabled; 0=disabled) Control the Comparator interrupt (1=enabled; 0=disabled) Control the external INT0A, INT0B, INT0C interrupt(1=enabled; 0=disabled) Control the external INT1 interrupt (1=enabled; 0=disabled) The Comparator request flag (1=active; 0=inactive) External interrupt INT0A, INT0B, INT0C request flag (1=active; 0=inactive) External interrupt INT1 request flag (1=active; 0=inactive) Unused bit, read as 0. INTC0 (0BH) Register Rev. 1.00 10 January 11, 2007 HT45RM03 Bit No. 0 1 2 3, 7 4 5 6 Label EPWMI ET0I ET1I 3/4 PWMF T0F T1F Function Control the PWM period interrupt (1=enabled; 0=disabled) Control the Timer/Event Counter 0 interrupt (1=enabled; 0=disabled) Control the Timer/Event Counter 1 interrupt (1=enabled; 0=disabled) Unused bit, read as 0. PWM period request flag (1=active; 0=inactive) Internal Timer/Event Counter 0 request flag (1=active; 0=inactive) Internal Timer/Event Counter 1 request flag (1=active; 0=inactive) INTC1 (1EH) Register During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (of course, if the stack is not full). To return from the interrupt subroutine, RET or RETI may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not. Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests the following table shows the priority that is applied. These can be masked by resetting the EMI bit. Interrupt Source Comparator output Interrupt External INT0A, INT0B, INT0C Interrupt External INT1 Interrupt PWM Period Interrupt Timer/Event Counter 0 Overflow Timer/Event Counter 1 Overflow Priority 1 2 3 4 5 6 Vector 04H OSC1 serviced. Once the interrupt request flags (EI0F, EI1F, CF, T0F, T1F, PWMF) are all set, they remain in the INTC1 or INTC0 respectively until the interrupts are serviced or cleared by a software instruction. It is recommended that a program does not use the CALL subroutine within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and enabling the interrupt is not well controlled, the original control sequence will be damaged once the CALL operates in the interrupt subroutine. Oscillator Configuration There are two oscillator circuits in the microcontroller. V DD 470pF OSC1 08H 0CH 10H 14H 18H OSC2 C r y s ta l O s c illa to r fS YS /4 RC OSC2 O s c illa to r System Oscillator Both are designed for system clocks, namely the RC oscillator and the Crystal oscillator, which are determined by options. No matter what oscillator type is selected, the signal provides the system clock. The HALT mode stops the system oscillator and ignores an external signal to conserve power. If an RC oscillator is used, an external resistor between OSC1 and VSS is required and the resistance must range from 24kW to 1MW. The system clock, divided by 4, is available on OSC2 with pull-high resistor, which can be used to synchronize external logic. The RC oscillator provides the most cost effective solution. However, the frequency of oscillation may vary with VDD, temperatures and the chip itself due to process variations. It is, therefore, not suitable for timing sensitive operations where an accurate oscillator frequency is desired. If the Crystal oscillator is used, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator, and no other external components are required. Instead of a crystal, a resona- The Comparator interrupt request flag (CF), external interrupt 1 request flag (EI1F), External Interrupt 0 request flag (EI0F), Enable Comparator 0 output interrupt bit (EC0I), Enable External interrupt 1 bit (EEI1), Enable External Interrupt 0 bit (EEI0), and enable master interrupt bit (EMI) make up of the Interrupt Control register 0 (INTC0) which is located at 0BH in the RAM. The PWM period interrupt request flag (PWMF), the Timer/Event Counter 1 interrupt request flag (T1F), the Timer/Event Counter 0 interrupt request flag (T0F), enable PWM period interrupt bit (EPWMI), enable Timer/Event Counter 1 interrupt bit (ET1I), and enable Timer/Event Counter 0 interrupt bit (ET0I), constitute the Interrupt Control register 1 (INTC1) which is located at 1EH in the RAM. EMI, EEI0, EEI1, ECI, ET0I, ET1I, and EPWMI are all used to control the enable/disable status of interrupts. These bits prevent the requested interrupt from being Rev. 1.00 11 January 11, 2007 HT45RM03 tor can also be connected between OSC1 and OSC2 to get a frequency reference, but two external capacitors in OSC1 and OSC2 are required (If the oscillating frequency is less than 1MHz). The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if the system enters the power down mode, the system clock is stopped, but the WDT oscillator still works with a period of approximately 65ms at 5V. The WDT oscillator can be disabled by options to conserve power. Watchdog Timer - WDT The clock source of WDT is implemented by a dedicated RC oscillator (WDT oscillator) or instruction clock (system clock divided by 4), decided by options. This timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by an option. If the Watchdog Timer is disabled, all the executions related to the WDT result in no operation. Once the internal WDT oscillator (RC oscillator with a period of 65ms at 5V normally) is selected, it is first divided by 256 (8-stage) to get the nominal time-out period of approximately 17ms at 5V. This time-out period may vary with temperatures, VDD and process variations. By invoking the WDT prescaler, longer time-out periods can be realized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of the WDTS) can give different time-out periods. If WS2, WS1, and WS0 are all equal to 1, the division ratio is up to 1:128, and the maximum time-out period is 2.1s at 5V seconds. If the WDT oscillator is disabled, the WDT clock may still come from the instruction clock and operate in the same manner except that in the HALT state the WDT may stop counting and lose its protecting purpose. In this situation the logic can only be restarted by external logic. The high nibble and bit 3 of the WDTS are reserved for users defined flags, which can be used to indicate some specified status. If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock. S y s te m C lo c k /4 W DT OSC O p tio n S e le c t 8 - b it C o u n te r WS2 0 0 0 0 1 1 1 1 WS1 0 0 1 1 0 0 1 1 WS0 0 1 0 1 0 1 0 1 Division Ratio 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 WDTS (09H) Register The WDT overflow under normal operation will initialize chip reset and set the status bit TO. But in the HALT mode, the overflow will initialize a warm reset, and only the Program Counter and SP are reset to zero. To clear the contents of WDT (including the WDT prescaler), three methods are adopted; external reset (a low level to RES), software instruction and a HALT instruction. The software instruction include CLR WDT and the other set - CLR WDT1 and CLR WDT2. Of these two types of instruction, only one can be active depending on the option - CLR WDT times selection option. If the CLR WDT is selected (i.e. CLRWDT times equal one), any execution of the CLR WDT instruction will clear the WDT. In the case that CLR WDT1 and CLR WDT2 are chosen (i.e. CLRWDT times equal two), these two instructions must be executed to clear the WDT; otherwise, the WDT may reset the chip as a result of time-out. Power Down Operation - HALT The HALT mode is initialized by the HALT instruction and results in the following... * The system oscillator will be turned off but the WDT oscillator keeps running (if the WDT oscillator is selected). * The contents of the on chip RAM and registers remain unchanged. * WDT will be cleared and recounted again (if the WDT clock is from the WDT oscillator). W D T P r e s c a le r 7 - b it C o u n te r 8 -to -1 M U X W D T T im e - o u t W S0~W S2 Watchdog Timer Rev. 1.00 12 January 11, 2007 HT45RM03 * All of the I/O ports maintain their original status. * The PDF flag is set and the TO flag is cleared. TO 0 u 0 1 1 PDF 0 u 1 u 1 RESET Conditions RES reset during power-up RES reset during normal operation RES wake-up HALT WDT time-out during normal operation WDT wake-up HALT The system can leave the HALT mode by means of an external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset causes a device initialization and the WDT overflow performs a warm reset. After the TO and PDF flags are examined, the reason for chip reset can be determined. The PDF flag is cleared by system power-up or executing the CLR WDT instruction and is set when executing the HALT instruction. The TO flag is set if the WDT time-out occurs, and causes a wake-up that only resets the program counter and SP; the others keep their original status. The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake up the device by the options. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If it is awakening from an interrupt, two sequences may happen. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the interrupt is enabled and the stack is not full, the regular interrupt response takes place. If an interrupt request flag is set to 1 before entering the HALT mode, the wake-up function of the related interrupt will be disabled. Once a wake-up event occurs, it takes 1024 tSYS (system clock period) to resume normal operation. In other words, a dummy period will be inserted after wake-up. If the wake-up results from an interrupt acknowledgment, the actual interrupt subroutine execution will be delayed by one or more cycles. If the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished. To minimize power consumption, all the I/O pins should be carefully managed before entering the HALT status. Reset There are three ways in which a reset can occur: * RES reset during normal operation * RES reset during HALT * WDT time-out reset during normal operation Note: u means unchanged To guarantee that the system oscillator is started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses when the system reset (power-up, WDT time-out or RES reset) or the system awakes from the HALT state. When a system reset occurs, the SST delay is added during the reset period. Any wake-up from HALT will enable the SST delay. The functional unit chip reset status are shown below. V DD 0 .0 1 m F * 100kW RES 10kW 0 .1 m F * Reset Circuit Note: * Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference. VDD RES S S T T im e - o u t C h ip R eset tS ST Reset Timing Chart The WDT time-out during HALT is different from other chip reset conditions, since it can perform a warm re set that resets only the program counter and SP, leaving the other circuits in their original state. Some registers remain unchanged during other reset conditions. Most registers are reset to the initial condition when the reset conditions are met. By examining the PDF and TO flags, the program can distinguish between different chip resets. HALT W DT RES W a rm R eset OSC1 SST 1 0 - b it R ip p le C o u n te r S y s te m R eset C o ld R eset Reset Configuration Rev. 1.00 13 January 11, 2007 HT45RM03 An extra option load time delay is added during system reset (power-up, WDT time-out at normal mode or RES reset). Program Counter Interrupt WDT Timer/Event Counter Input/Output Ports Stack Pointer 000H Disable Clear. After master reset, WDT begins counting Off Input mode Points to the top of the stack The registers states are summarized in the following table. Register MP0 MP1 ACC Program Counter TBLP TBLH STATUS WDTS INTC0 TMR0 TMR0C TMR1 TMR1C PA PAC PB PBC PC PCC PD PDC PWMH PWML PWMC MISC INTC1 ADRH ADRL ADCR ACSR CMPC OPAC Note: Reset (Power On) xxxx xxxx xxxx xxxx xxxx xxxx 000H xxxx xxxx -xxx xxxx --00 xxxx 0000 0111 -000 0000 0000 0000 00-0 1000 0000 0000 00-0 1000 1111 1111 1111 1111 1111 1111 1111 1111 0011 1111 --11 1111 ---- ---1 ---- ---1 0000 0000 ---- --00 0000 0000 -000 0000 -000 -000 xxxx xxxx x--- ---0100 0000 ---- --00 0000 0000 0000 0000 * stands for warm reset u stands for unchanged x stands for unknown 14 January 11, 2007 WDT Time-out RES Reset (Normal Operation) (Normal Operation) uuuu uuuu uuuu uuuu uuuu uuuu 000H uuuu uuuu -uuu uuuu --1u uuuu 0000 0111 -000 0000 0000 0000 00-0 1000 0000 0000 00-0 1000 1111 1111 1111 1111 1111 1111 1111 1111 0011 1111 --11 1111 ---- ---1 ---- ---1 0000 0000 ---- --00 0000 0000 -000 0000 -000 -000 xxxx xxxx x--- ---0100 0000 ---- --00 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu 000H uuuu uuuu -uuu uuuu --uu uuuu 0000 0111 -000 0000 0000 0000 00-0 1000 0000 0000 00-0 1000 1111 1111 1111 1111 1111 1111 1111 1111 0011 1111 --11 1111 ---- ---1 ---- ---1 0000 0000 ---- --00 0000 0000 -000 0000 -000 -000 xxxx xxxx x--- ---0100 0000 ---- --00 0000 0000 0000 0000 RES Reset (HALT) uuuu uuuu uuuu uuuu uuuu uuuu 000H uuuu uuuu -uuu uuuu --01 uuuu 0000 0111 -000 0000 0000 0000 00-0 1000 0000 0000 00-0 1000 1111 1111 1111 1111 1111 1111 1111 1111 0011 1111 --11 1111 ---- ---1 ---- ---1 0000 0000 ---- --00 0000 0000 -000 0000 -000 -000 xxxx xxxx x--- ---0100 0000 ---- --00 0000 0000 0000 0000 WDT Time-out (HALT)* uuuu uuuu uuuu uuuu uuuu uuuu 000H uuuu uuuu -uuu uuuu --11 uuuu uuuu uuuu -uuu uuuu uuuu uuuu uu-u uuuu uuuu uuuu uu-u uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu ---- ---u ---- ---u uuuu uuuu ---- --uu uuuu uuuu -uuu uuuu -uuu -uuu uuuu uuuu u--- ---uuuu uuuu ---- --uu uuuu uuuu uuuu uuuu Rev. 1.00 HT45RM03 Timer/Event Counter Two timer/event counters (TMR0,TMR1) are implemented in the microcontroller. The Timer/Event Counter 0 and Timer/Event Counter 1 contain 8-bit programmable count-up counter and the clock may come from an external source or an internal clock source. There are four registers related to the Timer/Event Counter 0; TMR0 (0DH), TMR0C (0EH), the Timer/Event Counter 1; TMR1(10H), TMR1C (11H). Writing TMR0/TMR1 makes the starting value be placed in the Timer/Event Counter 0/1 preload register and reading TMR0/1 get the contents of the Timer/Event Counter 0/1. The TMR0C and TMR1C are Timer/Event Counter control register 0/1, which defines the operating mode, counting enable or disable and an active edge. The T0M0/T1M0 and T0M1/T1M1 bits define the operation mode. The event count mode is used to count external events, which means that the clock source is from an external (TMR0, TMR1) pin. The timer mode functions as a normal timer with the clock source coming from the internal selected clock source. Finally, the pulse width measurement mode can be used to count the high or low level duration of the external signal (TMR0, TMR1), and the counting is based on the internal selected clock source. In the event count or timer mode, the Timer/Event Counter 0/1 starts counting at the current contents in the timer/event counter and ends at FFH. Once an overflow occurs, the counter is reloaded from the timer/event counter preload register, and generates an interrupt request flag (T0F; bit 5 of the INTC1, T1F; bit 6 of the INTC1). In the pulse width measurement mode with the values of the T0ON/T1ON and T0E/T1E bits equal to 1, after the fS YS TMR0/TMR1 has received a transient from low to high (or high to low if the T0E/T1E bit is 0), it will start counting until the TMR0/TMR1 returns to the original level and resets the T0ON/T1ON. The measured result remains in the timer/event counter even if the activated transient occurs again. In other words, only 1-cycle measurement can be made until the T0ON/T1ON is set. The cycle measurement will re-function as long as it receives further transient pulse. In this operation mode, the timer/event counter begins counting not according to the logic level but to the transient edges. In the case of counter overflows, the counter is reloaded from the timer/event counter register and issues an interrupt request, as in the other two modes, i.e., event and timer modes. To enable the counting operation, the Timer ON bit (T0ON; bit 4 of the TMR0C or T1ON; bit 4 of the TMR1C) should be set to 1. In the pulse width measurement mode, the T0ON/T1ON is automatically cleared after the measurement cycle is completed. But in the other two modes, the T0ON/T1ON can only be reset by instructions. The overflow of the Timer/Event Counter 0/1 is one of the wake-up sources and the Timer/Event Counter 0/1 can also be applied to a PFD (Programmable Frequency Divider) output at PA3 by software control. Only one PFD (PFD0 or PFD1) can be applied to PA3 by software. No PFD0 PFD1 PFD M U X T Q PFD P D 0 D a ta C T R L S o u r c e O p tio n PFD Source Option 7 - s ta g e P r e s c a le r 8 -1 M U X T0PSC 2~T0PSC 0 TM R0 T0E T0M 1 T0M 0 T0O N P u ls e W id th M e a s u re m e n t M o d e C o n tro l 8 - b it T im e r /E v e n t C o u n te r (T M R 0 ) PFD0 O v e r flo w to In te rru p t f IN T D a ta B u s T0M 1 T0M 0 8 - b it T im e r /E v e n t C o u n te r R e lo a d P r e lo a d R e g is te r Timer/Event Counter 0 fS YS 7 - s ta g e P r e s c a le r 8 -1 M U X T1PSC 2~T1PSC 0 TM R1 T1E T1M 1 T1M 0 T1O N P u ls e W id th M e a s u re m e n t M o d e C o n tro l 8 - b it T im e r /E v e n t C o u n te r (T M R 1 ) PFD1 O v e r flo w to In te rru p t f IN T D a ta B u s T1M 1 T1M 0 8 - b it T im e r /E v e n t C o u n te r R e lo a d P r e lo a d R e g is te r Timer/Event Counter 1 Rev. 1.00 15 January 11, 2007 HT45RM03 matter what the operation mode is, writing a 0 to ET0I or ET1I disables the related interrupt service. When the PFD function is selected, executing SET [PA].3 instruction to enable the PFD output and executing CLR [PA].3 instruction to disable the PFD output. After this procedure, the timer/event function can be operated normally. The bit0~bit2 of the TMR0C/TMR1C can be used to define the pre-scaling stages of the internal clock sources of timer/event counter. The definitions are as shown. The overflow signal of timer/event counter can be used to generate the PFD signal. In the case of timer/event counter off condition, writing data to the timer/event counter preload register also reloads that data to the timer/event counter. But if the timer/event counter is turn-on, data written to the Bit No. Label timer/event counter is kept only in the timer/event counter preload register. The timer/event counter still continues its operation until an overflow occurs. When the timer/event counter (reading TMR0/TMR1) is read, the clock is blocked to avoid errors, as this may results in a counting error. Blocking of the clock should be taken into account by the programmer. It is strongly recommended to load a desired value into the TMR0/TMR1 register first, before turning on the related timer/event counter, for proper operation since the initial value of TMR0/TMR1 is unknown. Due to the timer/event scheme, the programmer should pay special attention on the instruction to enable then disable the timer for the first time, whenever there is a need to use the timer/event function, to avoid unpredictable result. Function 0~2 To define the prescaler stages, T0PSC2, T0PSC1, T0PSC0= 000: fINT=fSYS 001: fINT=fSYS/2 010: fINT=fSYS/4 T0PSC0~ 011: fINT=fSYS/8 T0PSC2 100: fINT=fSYS/16 101: fINT=fSYS/32 110: fINT=fSYS/64 111: fINT=fSYS/128 T0E T0ON 3/4 T0M0 T0M1 To define the TMR0 active edge of Timer/Event Counter 0 (0=active on low to high; 1=active on high to low) To enable or disable Timer 0 counting (0=disabled; 1=enabled) Unused bit, read as 0 To define the operating mode, T0M1, T0M0= 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMR0C (0EH) Register 3 4 5 6 7 Bit No. Label Function 0~2 To define the prescaler stages, T1PSC2, T1PSC1, T1PSC0= 000: fINT=fSYS 001: fINT=fSYS/2 010: fINT=fSYS/4 T1PSC0~ 011: fINT=fSYS/8 T1PSC2 100: fINT=fSYS/16 101: fINT=fSYS/32 110: fINT=fSYS/64 111: fINT=fSYS/128 T1E T1ON 3/4 T1M0 T1M1 To define the TMR1 active edge of Timer/Event Counter 1 (0=active on low to high; 1=active on high to low) To enable or disable Timer 1 counting (0=disabled; 1=enabled) Unused bit, read as0 To define the operating mode, T1M1, T1M0= 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMR1C (11H) Register 3 4 5 6 7 Rev. 1.00 16 January 11, 2007 HT45RM03 Input/Output Ports There are 23 bidirectional input/output lines in the microcontroller, labeled as PA, PB, PC and PD, which are mapped to the data memory of [12H], [14H], [16H] and [18H] respectively. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction MOV A,[m] (m=12H, 14H, 16H or 18H). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Each I/O line has its own control register (PAC, PBC, PCC, PDC) to control the input/output configuration. With this control register, CMOS output or schmitt trigger input with or without pull-high resistor structures can be reconfigured dynamically (i.e. on-the-fly) under software control. To function as an input, the corresponding latch of the control register must write 1. The input source also depends on the control register. If the control register bit is 1, the input will read the pad state. If the control register bit is 0, the contents of the latches will move to the internal bus. The latter is possible in the read-modify-write instruction. For output function, CMOS is the only configuration. These control registers are mapped to locations 13H, 15H, 17H and 19H. After a chip reset, these input/output lines remain at high levels or floating state (dependent on pull-high options). Each bit of these input/output latches can be set or cleared by SET [m].i and CLR [m].i (m=12H, 14H, 16H or 18H) instructions. Some instructions first input data and then follow the output operations. For example, SET [m].i, CLR [m].i, CPL [m], CPLA [m] read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Each line of port A has the capability of waking-up the device. The highest 7-bit of port D are not physically implemented; on reading them a 0 is returned whereas writing then results in a no-operation. See Application note. Each I/O port has a pull-high option. Once the pull-high option is selected, the I/O port has a pull-high resistor, otherwise, theres none. Take note that a non-pull-high I/O port operating in input mode will cause a floating state. The PD0 is pin-shared with the PFD signal. If the PFD function is selected, the output signal in output mode of PD0 will be the PFD signal generated by the timer/event counter overflow signal. The input mode is always remaining its original functions. Once the PFD option is selected, the PFD output signal is controlled by PD0 data register only. Writing 1 to PD0 data register will Rev. 1.00 17 enable the PFD output function and writing 0 will force the PD0 to remain at 0. The I/O functions of PD0 are shown below. I/O I/P Mode (Normal) PD0 Note: Logical Input O/P (Normal) Logical Output I/P (PFD) Logical Input O/P (PFD) PFD (Timer on) The PFD frequency is the timer/event counter overflow frequency divided by 2. The PA4, PA5, PA6, PA7 and PB7 are pin-shared with INT0A, INT0B, INT0C, INT1 and TMR0/TMR1 pins respectively. The CVINN and COUT are pin-shared with PA1, PA2 and PA3. Once the Comparator function is used, the internal registers related to PA1, PA2 cannot be used, PA3 can be used as input only (if the COUTEN is 1), and the PA1, PA2 I/O function, PA3 output function and pull-high resistor are disabled automatically(if the COUTEN is 1). Once the Comparator function is used, the PA3 is the GPIO when the COUTEN is 0. Software instructions determine the Comparator function to be used. CMPEN COUTEN 0 X PA1, PA2, PA3 PA1, PA2, PA3 is GPIO PA1, PA2 is Comparator input pin and PA3 is GPIO. PA3 falling edge can generate the Comparator interrupt. PA1, PA2 is comparator input pin and PA3 is Comparator output pin. PA3 can read the Comparateor output status. 1 0 1 1 The OPVINP, OPVINN and OPOUT are pin-shared with PA0, PB3/AN3 and PB2/AN2 respectively. Once the OPA function is used, the internal registers related to PA0, PB3 and PB2 cannot be used, and the I/O function and pull-high resistor are disabled automatically. Software instructions determine the OPA function to be used. OPAEN 0 PA0, PA3/AN3, PB2/AN2 PA0 is GPIO and PB2/AN2, PB3/AN3 is GPIO or analog ADC input by ADCR register. PA0, PB3/AN3 is OPA input pin and PB2/AN2 is OPA output pin. The PB2/AN2 and PB3/AN3 can be analog ADC input if the related ADC function is enabled. 1 The PB can also be used as A/D converter inputs. The A/D function will be described later. Once a PB line is selected as an A/D input (by using software control), the I/O function and pull-high resistor are disabled automatically. The PWM0~PWM2 and PWM0~PWM2 output function are pin-shared with PC0, PC2, PC4 and PC1, PC3, PC5 respectively by software control. January 11, 2007 HT45RM03 There is a PWM function shared with PC0~PC5. If the PWM function is enabled, the PWM0~PWM2 and PWM0~PWM2 signal will appear on PC0, PC2, PC4 and PC1, PC3, PC5 respectively (if PC0/PC1/PC2/PC3/ PC4/PC5 is operating in output mode). Writing 1 to PC0/PC2/PC4 data register will enable the PWM0/PWM1/PWM2 output function and writing PWMEN 0 1 1 1 1 PC7 X 0 0 1 1 PC6 X 0 1 0 1 0 will force the PC0/PC2/PC4 to remain at 0 (inactive state). Writing 1 to PC1/PC3/PC5 data register will enable the PWM0/PWM1/PWM2 output function and writing 0 will force the PC1/PC3/PC5 to remain at 0 inactive state). The I/O functions of PC0~PC5 are as shown. PC4 Logical Logical Logical PWM PWM PC2 Logical Logical PWM Logical PWM PC0 Logical PWM Logical Logical PWM PC0, PC2, PC4 Output Function PWMCEN 0 1 1 1 1 PC7 X 0 0 1 1 PC6 X 0 1 0 1 PC5 Logical Logical Logical PWM PWM PC3 Logical Logical PWM Logical PWM PC1 Logical PWM Logical Logical PWM PC1, PC3, PC5 Output Function There is only one channel PWM and PWM output at a time. The PC.6 and PC.7 is to determine which PWM0/PWM0, PWM1/PWM1 or PWM2/PWM2 appeared to the PC0/PC1, PC2/PC3 or PC4/PC5. PC7, PC6 PWM (PWMEN=1) PC0/PWM0 is PWM output, if the PC0 is output mode (PCC.0 = 0). The PC2 and PC4 are the GPIO. Writing 1 to PC0 data register will enable the PWM0 output function and writing 0 will force the PC0 to remain at PWM0 output inactive state. PC2/PWM1 is PWM output, if the PC2 is output mode (PCC.2 = 0). The PC0 and PC4 are the GPIO. Writing 1 to PC2 data register will enable the PWM1 output function and writing 0 will force the PC2 to remain at PWM1 output inactive state. PC4/PWM2 is PWM output, if the PC4 is output mode (PCC.4 = 0). The PC0 and PC2 are the GPIO. Writing 1 to PC4 data register will enable the PWM2 output function and writing 0 will force the PC4 to remain at PWM2 output inactive state. PC0/PWM0, PC2/PWM1 and PC4/PWM2 are PWM output, if the PC0, PC2 and PC4 are output mode (PCC.0, 2, 4 = 0). Writing 1 to PC0/PC2/PC4 data register will enable the PWM0/PWM1/PWM2 output function and writing 0 will force the PC0/PC2/PC4 to remain at PWM output inactive state. PWM (PWMCEN=1) PC1/PWM0 is PWM output, if the PC1 is output mode (PCC.1 = 0). The PC3 and PC5 are the GPIO. Writing 1 to PC1 data register will enable the PWM0 output function and writing 0 will force the PC1 to remain at PWM0 output inactive state. PC3/PWM1 is PWM output, if the PC3 is output mode (PCC.3 = 0). The PC1 and PC5 are the GPIO. Writing 1 to PC3 data register will enable the PWM1 output function and writing 0 will force the PC3 to remain at PWM1 output inactive state. PC5/PWM2 is PWM output, if the PC5 is output mode (PCC.5 = 0). The PC1 and PC3 are the GPIO. Writing 1 to PC5 data register will enable the PWM2 output function and writing 0 will force the PC5 to remain at PWM2 output inactive state. PC1/PWM0, PC3/PWM1 and PC5/PWM2 are PWM output, if the PC1, PC3 and PC5 are output mode (PCC.1, 3, 5 = 0). Writing 1 to PC1/PC3/PC5 data register will enable the PWM0/PWM1/PWM2 output function and writing 0 will force the PC1/PC3/PC5 to remain at PWM output inactive state. 0, 0 0, 1 1, 0 1, 1 Note: If PWMEN=0, the PWM function output is disable and the PC0, PC2 and PC4 are the GPIO. If PWMCEN=0, the PWM function output is disable and the PC1, PC3 and PC5 are the GPIO. The PWMEN and PWMCEN are independent to enable or disable the PWM and PWM Complement function. If the PCC.x is 1, the PC.x is input mode. x is from 0~5. Rev. 1.00 18 January 11, 2007 HT45RM03 It is recommended that unused or not bonded out I/O lines should be set as output pins by software instruction to avoid consuming power under input floating state. V D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r D a ta B it Q D CK S Q M U X C o n tr o l B it P u ll- h ig h Q D CK S Q DD W r ite D a ta R e g is te r P C 0 /P C 1 /P C 2 /P C 3 /P C 4 /P C 5 /P D 0 P W M 0 /P W M 0 /P W M 1 /P W M 1 /P W M 2 /P W M 2 /P F D M U X R e a d D a ta R e g is te r S y s te m IN T 0 A IN T 0 B IN T 0 C IN T 1 T M R 0 /T M R 1 fo fo fo fo fo rP rP rP rP rP W a k e -u p ( P A o n ly ) On On On On B7On A4 A5 A6 A7 ly ly ly ly ly PA PA PA PA PA PA PA PA PB PB PB PB PB PC PC PC PC PC PC PD 0 /O 1 /C 2 /C 3 /C 4 /IN 5 /IN 6 /IN 7 /IN 0 /A 2 /A 3 /A 4 /A 7 /A 0 /P 1 /P 2 /P 3 /P 4 /P 5 /P 0 /P P V IN V IN P V IN N OUT T0A T0B T0C T1 N0~P N 2 /O N 3 /O N4~P N 7 /T WM0 WM0 WM1 WM1 WM2 WM2 FD P B1 PO PV B6 MR /A N 1 UT IN N /A N 6 0 /T M R 1 O P0~O P7 Input/Output Ports PWM The microcontroller is provided with three channel PWM and Complementary PWM output shared with PC0~PC5, named PWM0~PWM2 and PWM0~PWM2, with standard 10 bits output, (9+1), (8+2), or (7+3) mode (configuration option determined). The PWM function provides output with a varied frequency and duty cycle by setting particular values into PWMC and PWML, PWMH registers. The frequency source of the PWM counter comes from fPWM. The fPWM clock source can be chosen from fSYS~fSYS/8 (software option determined). The PWM channel has their data registers denoted as PWMH (1AH) and PWML (1BH). These two registers define the PWM output duty cycle. The PWMH is an 8-bit register, and it is a higher-order data register, the PWML is a lower-order register and two bits (bit1~bit0) are provided in this register. The PWM duty cycle is specified by writing to these two PWM data registers, writing PWML will only put the written data to an internal lower-order byte buffer (2-bit) and writing PWMH will transfer the specified data and the contents of the lower-order byte buffer to PWMH and PWML registers, respectively. Once the PC0~PC5 is selected as the PWM and Complementary PWM outputs and the output function of PC0~PC5 is enabled (PCC.0 ~ PCC.5 = 0), writing 1 to PC0, PC2 and PC4 register will enable the PWM output function and writing 0 will force the PC0, PC2 and PC4 stay at inactive state (0 if the PWMLEV option is select active high). Writing 1 to PC1, PC3 and PC5 register will enable the Complementary PWM output function and writing 0 will force the PC1, PC3 and PC5 stay at inactive state (0 if the PWMCLEV option is select active high). The PWM clock source can be chosen form fSYS~fSYS/8 (dependent on software option). When the fPWM clock source is selected from fSYS~fSYS/8, the PWM function provides with a fixed frequency output (fSYS/1024~ (fSYS/8192). The PWM output provides standard 10-bit, (9+1), (8+2) and (7+3) output mode, its duty cycle is decided by writing to the PWMH and PWML registers, the waveform of PWMH output is as shown. When the PWM output function is enabled (writing 1 to PC0~PC5 register, when PWM and Complementary PWM output function is enable) and the fPWM clock source is selected from PWM prescaler, the value of PWMPSC0~PWMPSC1, PWML and PWMH can be written to at any time even if the PWM and Complementary PWM output is running. Rev. 1.00 19 January 11, 2007 HT45RM03 Register PWMH PWML Bit 7 D9 3/4 Bit 6 D8 3/4 Bit 5 D7 3/4 Bit 4 D6 3/4 Bit 3 D5 3/4 Bit 2 D4 3/4 Bit 1 D3 D0 Bit 0 D2 D1 PWMH (1AH), PWML (1BH) Register A (9+1) bits mode PWM cycle is divided into two modulation cycles (modulation cycle 0~modulation cycle 1). Each modulation cycle has 512 PWM input clock period. In a (9+1) bit PWM function, the contents of the PWM register is divided into two groups. Group 1 of the PWM registers are denoted by DC which are the values of PWMH.7~PWMH.0 and PWML.1 (9 bit from PWMH~PWML.1). The group 2 is denoted by AC which is the value of PWML.0. In a (9+1) bits mode PWM cycle, the duty cycle of each modulation cycle is shown in the table. Parameter Modulation Cycle I (i=0~1) iAC DC/512 AC0~AC1 i fPWM/1024 [PWM]/1024 fP WM /2 [P W M ] = 1 0 0 PW M PW M 1 0 0 /1 0 2 4 M o d u la tio n P e r io d : 1 0 2 4 /fP PW M F u ll C y c le : 1 0 2 4 /fP WM WM 1 0 0 /1 0 2 4 1 0 0 /1 0 2 4 Standard 10 Bit PWM Mode Rev. 1.00 20 January 11, 2007 HT45RM03 fP WM /2 [P W M ] = 1 0 0 PW M [P W M ] = 1 0 1 PW M [P W M ] = 1 0 2 PW M [P W M ] = 1 0 3 PW M PW M 5 2 /5 1 2 M o d u la tio n P e r io d : 5 1 2 /fP WM 5 0 /5 1 2 5 0 /5 1 2 5 0 /5 1 2 5 1 /5 1 2 5 0 /5 1 2 5 1 /5 1 2 5 1 /5 1 2 5 1 /5 1 2 5 1 /5 1 2 5 1 /5 1 2 5 2 /5 1 2 PW M C y c le : 1 0 2 4 /fP WM (9+1) PWM Mode fP WM /2 [P W M ] = 1 0 0 PW M [P W M ] = 1 0 1 PW M [P W M ] = 1 0 2 PW M [P W M ] = 1 0 3 PW M PW M 2 6 /2 5 6 M o d u la tio n P e r io d : 2 5 6 /fP WM 2 5 /2 5 6 2 5 /2 5 6 2 5 /2 5 6 2 5 /2 5 6 2 5 /2 5 6 2 6 /2 5 6 2 5 /2 5 6 2 5 /2 5 6 2 5 /2 5 6 2 6 /2 5 6 2 6 /2 5 6 2 6 /2 5 6 2 5 /2 5 6 2 5 /2 5 6 2 6 /2 5 6 2 6 /2 5 6 2 6 /2 5 6 2 5 /2 5 6 2 6 /2 5 6 PW M F u ll P e r io d : 1 0 2 4 /fP WM (8+2) PWM Mode fP WM /2 [P W M ] = 1 1 2 PW M 1 4 /1 2 8 1 4 /1 2 8 1 4 /1 2 8 1 4 /1 2 8 1 4 /1 2 8 1 4 /1 2 8 1 4 /1 2 8 1 4 /1 2 8 1 4 /1 2 8 1 4 /1 2 8 [P W M ] = 1 1 3 PW M 1 5 /1 2 8 1 4 /1 2 8 1 4 /1 2 8 1 4 /1 2 8 1 4 /1 2 8 1 4 /1 2 8 1 4 /1 2 8 1 4 /1 2 8 1 5 /1 2 8 1 4 /1 2 8 [P W M ] = 1 1 4 PW M 1 5 /1 2 8 1 5 /1 2 8 1 4 /1 2 8 1 4 /1 2 8 1 4 /1 2 8 1 4 /1 2 8 1 4 /1 2 8 1 4 /1 2 8 1 5 /1 2 8 1 5 /1 2 8 [P W M ] = 1 1 5 PW M 1 5 /1 2 8 1 5 /1 2 8 1 5 /1 2 8 1 4 /1 2 8 1 4 /1 2 8 1 4 /1 2 8 1 4 /1 2 8 1 4 /1 2 8 1 5 /1 2 8 1 5 /1 2 8 [P W M ] = 1 1 6 PW M 1 5 /1 2 8 1 5 /1 2 8 1 5 /1 2 8 1 5 /1 2 8 1 4 /1 2 8 1 4 /1 2 8 1 4 /1 2 8 1 4 /1 2 8 1 5 /1 2 8 1 5 /1 2 8 [P W M ] = 1 1 7 PW M 1 5 /1 2 8 1 5 /1 2 8 1 5 /1 2 8 1 5 /1 2 8 1 5 /1 2 8 1 4 /1 2 8 1 4 /1 2 8 1 4 /1 2 8 1 5 /1 2 8 1 5 /1 2 8 [P W M ] = 1 1 8 PW M 1 5 /1 2 8 1 5 /1 2 8 1 5 /1 2 8 1 5 /1 2 8 1 5 /1 2 8 1 5 /1 2 8 1 4 /1 2 8 1 4 /1 2 8 1 5 /1 2 8 1 5 /1 2 8 [P W M ] = 1 1 9 PW M 1 5 /1 2 8 PW M 1 5 /1 2 8 1 5 /1 2 8 WM 1 5 /1 2 8 1 5 /1 2 8 1 5 /1 2 8 1 5 /1 2 8 1 4 /1 2 8 1 5 /1 2 8 1 5 /1 2 8 M o d u la tio n P e r io d : 1 2 8 /fP PW M F u ll P e r io d : 1 0 2 4 /fP WM (7+3) PWM Mode Rev. 1.00 21 January 11, 2007 HT45RM03 PWM and Complementary PWM output channels are shown below. PWMEN 0 1 1 1 1 PC7 X 0 0 1 1 PC6 X 0 1 0 1 PWM Disable PWM0, PWM1, PWM2 Enable PWM0 Enable PWM1 Enable PWM2 Enable PWM0, PWM1, PWM2 PWMCEN 0 1 1 1 1 PC7 X 0 0 1 1 PC6 X 0 1 0 1 PWM Disable PWM0, PWM1, PWM2 Enable PWM0 Enable PWM1 Enable PWM2 Enable PWM0, PWM1, PWM2 The PWM period interrupt will occur, when PWM counter is overflow. The PWM period interrupt is shown below. PWM and Complementary PWM output are shown below. PC PC 0: 1: 0, 1, PW PW PC PC M M 2 orPC4 3 orPC5 In a c tiv e A c tiv e PW M 0,PW M 1 orPW M 2 PW M 0,PW M 1 orPW M 2 PC PC 0: 1: 0, 1, PW PW PC PC M M 2 orPC4 3 orPC5 In a c tiv e A c tiv e PW M 0,PW M 1 orPW M 2 PW M 0,PW M 1 orPW M 2 PWM and Complementary PWM Output Without Dead Time (PWMLEV & PWMCLEV = 0 & 0) PC PC 0: 1: 0, 1, PW PW PC PC M M 2 orPC4 3 orPC5 In a c tiv e A c tiv e PW M 0,PW M 1 orPW M 2 PW M 0,PW M 1 orPW M 2 PC PC 0: 1: 0, 1, PW PW PC PC M M 2 orPC4 3 orPC5 In a c tiv e A c tiv e PW M 0,PW M 1 orPW M 2 PW M 0,PW M 1 orPW M 2 PWM and Complementary PWM Output Without Dead Time (PWMLEV & PWMCLEV = 0 & 1) Rev. 1.00 22 January 11, 2007 HT45RM03 PC PC 0: 1: 0, 1, PW PW PC PC M M 2 orPC4 3 orPC5 In a c tiv e A c tiv e PW M 0,PW M 1 orPW M 2 PW M 0,PW M 1 orPW M 2 PC PC 0: 1: 0, 1, PW PW PC PC M M 2 orPC4 3 orPC5 In a c tiv e A c tiv e PW M 0,PW M 1 orPW M 2 PW M 0,PW M 1 orPW M 2 PWM and Complementary PWM Output Without Dead Time (PWMLEV & PWMCLEV = 1 & 0) PC PC 0: 1: 0, 1, PW PW PC PC M M 2 orPC4 3 orPC5 In a c tiv e A c tiv e PW M 0,PW M 1 orPW M 2 PW M 0,PW M 1 orPW M 2 PC PC 0: 1: 0, 1, PW PW PC PC M M 2 orPC4 3 orPC5 In a c tiv e A c tiv e PW M 0,PW M 1 orPW M 2 PW M 0,PW M 1 orPW M 2 PWM and Complementary PWM Output Without Dead Time (PWMLEV & PWMCLEV = 1 & 1) The Complementary PWM output provides with dead time function. The dead time is from fSYS/2~fSYS/16. The ComplePC PC 0: 1: 0, 1, PW PW PC PC M M 2 orPC4 3 orPC5 In a c tiv e A c tiv e PW M P e r io d PW M D u ty PW M 0,PW M 1 orPW M 2 PW M 0,PW M 1 orPW M 2 PW M In te rru p t PWM and Complementary PWM Output Without Dead Time (PWMLEV & PWMCLEV = 0 & 0) Rev. 1.00 23 January 11, 2007 HT45RM03 mentary PWM output with dead time is shown below. DT PW M P e r io d DT PC PC 0: 1: 0, 1, PW PW PC PC M M 2 orPC4 3 orPC5 In a c tiv e A c tiv e PW M 0,PW M 1 orPW M 2 PW M 0,PW M 1 orPW M 2 PW M D u ty PWM and Complementary PWM Output Without Dead Time (PWMLEV & PWMCLEV = 0 & 0) Bit No. 0 1 2 3 4 5 6 7 Label PWMEN PWMCEN DTEN PWMPS0 PWMPS1 PWMPS2 PWMDT0 PWMDT1 Function To enable/disable PWM output (0=disabled; 1=enabled) To enable/disable PWM Complementary output (0=disabled; 1=enabled) To enable/disable PWM Complementary output with dead time (0=without dead time; 1=with dead time) These three bits select the PWM clock prescaler rate. These two bits select the PWM Complementary output dead time PWMC (1CH) Register The bits 3~5 of the PWM control register (PWMC) can be used to define the pre-scaling stages of the PWM clock. PWMPS2 0 0 0 0 1 1 1 1 PWMPS1 0 0 1 1 0 0 1 1 PWMPS0 0 1 0 1 0 1 0 1 To Define the Prescaler Stages fPWM=fSYS fPWM=fSYS/2 fPWM=fSYS/4 fPWM=fSYS/8 fPWM=fSYS/16 fPWM=fSYS/32 fPWM=fSYS/64 fPWM=fSYS/128 PWM period according different PWM prescaler rate bits and system clock. PWMPS2 0 0 0 0 1 1 1 1 PWMPS1 0 0 1 1 0 0 1 1 PWMPS0 0 1 0 1 0 1 0 1 fSYS=4MHz 3.91 1.95 0.98 0.49 0.24 0.12 0.06 0.03 fSYS=8MHz 7.81 3.91 1.95 0.98 0.49 0.24 0.12 0.06 fSYS=12MHz 11.72 5.86 2.93 1.46 0.73 0.37 0.18 0.09 kHz Unit 10-bit PWM Full Frequency (fSYS is 4, 8, 12MHz) Rev. 1.00 24 January 11, 2007 HT45RM03 The bits 7~6 of the PWM control register (PWMC) can be used to define the PWM Complementary output dead time. PWMDT1 0 0 1 1 PWMDT0 0 1 0 1 To Define the PWM Complementary Output Dead Time Dead Time=fSYS/2 Dead Time=fSYS/4 Dead Time=fSYS/8 Dead Time=fSYS/16 PWMDT1 0 0 1 1 PWMDT0 0 1 0 1 fSYS=4MHz 0.50 1.00 2.00 4.00 fSYS=8MHz 0.25 0.50 1.00 2.00 fSYS=12MHz 0.17 0.33 0.67 1.33 Unit ms Dead Time Setting (fSYS is 4, 8, 12MHz) PWM Options There are two options to define the PWM and PWM Complementary output level. These two bits can be read by software. Options PWM output level selection; PWMLEV. Description This option is to determine the PWM output level. Active Low or Active High selection. Disable this bit to 0, the PWM output will be defined as an active high output, Enable this bit to 1, the PWM output will be defined as an active low output. If the PWM function disable, this bit is invalid. This option is to determine the PWM Complementary output level. Active low or active high selection. Disable this bit to 0, the PWM Complementary outPWM Complementary output level put will be defined as an active high output, Enable this bit to 1, the PWM selection; PWMCLEV. Complementary output will be defined as an active low output. If the PWM Complementary function disable, this bit is invalid. P C 0 /P W M 0 PW M PW MH PW ML PW M PW M D e a d T im e C o n tr o l PW M PW MEN PW MCEN PW M C o m p le m e n ta r y O u tp u t PW M C TR L,PC 7, PC 6,PW M C LEV P C 1 /P W M 0 P C 3 /P W M 1 P C 5 /P W M 2 P e r io d In te r r u p t PW M O u tp u t P C 2 /P W M 1 P C 4 /P W M 2 PW M C TR L,PC 7, PC 6,PW M LEV PWM Rev. 1.00 25 January 11, 2007 HT45RM03 A/D Converter The 8 channels and 9-bit resolution A/D converter are implemented in this microcontroller. The reference voltage is VDD. The A/D converter contains 4 special registers which are; ADRL (20H), ADRH (21H), ADCR (22H) and ACSR (23H). The ADRH and ADRL are A/D result register higher-order byte and lower-order byte and are read-only. After the A/D conversion is completed, the ADRH and ADRL should be read to get the conversion result data. The ADCR is an A/D converter control register, which defines the A/D channel number, analog channel select, start A/D conversion control bit and the end of A/D conversion flag. If the users want to start an A/D conversion, define PB configuration, select the converted analog channel, and give START bit a raising edge and falling edge (0(R)1(R)0). At the end of A/D conversion, the EOCB bit is cleared and an A/D converter interrupt occurs (if the A/D converter interrupt is enabled). The ACSR is A/D clock setting register, which is used to select the A/D clock source. The A/D converter control register is used to control the A/D converter. The bit2~bit0 of the ADCR are used to select an analog input channel. There are a total of eight channels to select. The bit5~bit3 of the ADCR are used to set PB configurations. PB can be an analog input or as digital I/O line decided by these 3 bits. Once a PB line is selected as an analog input, the I/O functions and pull-high resistor of this I/O line are disabled and the A/D converter circuit is power on. The EOCB bit (bit6 of the ADCR) is end of A/D conversion flag. Check this bit to know when A/D conversion is completed. The START bit of the ADCR is used to begin the conversion of the A/D converter. Giving START bit a rising edge and falling edge means that the A/D conversion has started. In order to ensure the A/D conversion is completed, the START should remain at 0 until the EOCB is cleared to 0 (end of A/D conversion). Bit No. Label Selects the A/D converter clock source 00= system clock/2 01= system clock/8 10= system clock/32 11= undefined Unused bit, read as 0 ACSR (23H) Register Bit No. 0 1 2 3 4 5 Label ACS0 ACS1 ACS2 PCR0 PCR1 PCR2 Defines the analog channel select. Function Function 0 1 ADCS0 ADCS1 2~7 3/4 Defines the port B configuration select. If PCR0, PCR1 and PCR2 are all 0, the ADC circuit is power off to reduce power consumption Indicates end of A/D conversion. (0 = end of A/D conversion) Each time bits 3~5 change state the A/D should be initialized by issuing a START signal, otherwise the EOCB flag may have an undefined condition. See Important note for A/D initialization. Starts the A/D conversion. (0(R)1(R)0= start; 0(R)1= Reset A/D converter and set EOCB to 1) ADCR (22H) Register 6 EOCB 7 START PCR2 0 0 0 0 1 1 1 1 PCR1 0 0 1 1 0 0 1 1 PCR0 0 1 0 1 0 1 0 1 7 PB7 PB7 PB7 PB7 PB7 PB7 PB7 AN7 6 PB6 PB6 PB6 PB6 PB6 PB6 PB6 AN6 5 PB5 PB5 PB5 PB5 PB5 PB5 AN5 AN5 4 PB4 PB4 PB4 PB4 PB4 AN4 AN4 AN4 3 PB3 PB3 PB3 PB3 AN3 AN3 AN3 AN3 2 PB2 PB2 PB2 AN2 AN2 AN2 AN2 AN2 1 PB1 PB1 AN1 AN1 AN1 AN1 AN1 AN1 0 PB0 AN0 AN0 AN0 AN0 AN0 AN0 AN0 Port B Configuration Rev. 1.00 26 January 11, 2007 HT45RM03 ACS2 0 0 0 0 1 1 1 1 ACS1 0 0 1 1 0 0 1 1 ACS0 0 1 0 1 0 1 0 1 Analog Input Channel Selection Bit 7 of the ACSR register is used for test purposes only and must not be used for other purposes by the application program. Bit1 and bit0 of the ACSR register are used to select the A/D clock source. When the A/D conversion has completed, the A/D interrupt request flag will be set. The EOCB bit is set to 1 when the START bit is set from 0 to 1. Important Note for A/D initialization: Special care must be taken to initialize the A/D converter each time the Port B A/D channel selection bits are modified, otherwise the EOCB flag may be in an undefined condition. An A/D initialization is implemented by setting the START bit high and then clearing it to zero within 10 instruction cycles of the Port B channel selection bits being modified. Note that if the Port B channel selection bits are all cleared to zero then an A/D initialization is not required. Register ADRL ADRH Note: Bit7 D0 D8 Bit6 3/4 D7 Bit5 3/4 D6 Bit4 3/4 D5 Bit3 3/4 D4 Bit2 3/4 D3 Bit1 3/4 D2 Bit0 3/4 D1 Analog Channel AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 D0~D8 is A/D conversion result data bit LSB~MSB. ADRL (20H), ADRH (21H) Register The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to determine when the conversion is complete. Example: using EOCB Polling Method to detect end of conversion ; disable ADC interrupt mov mov mov mov a,00000001B ACSR,a a,00100000B ADCR,a : : : Start_conversion: clr set clr START START START ; reset A/D ; start A/D ; As the Port B channel bits have changed the following START ; signal (0-1-0) must be issued within 10 instruction cycles ; setup the ACSR register to select fSYS/8 as the A/D clock ; setup ADCR register to configure Port PB0~PB3 as A/D inputs ; and select AN0 to be connected to the A/D converter Rev. 1.00 27 January 11, 2007 HT45RM03 Polling_EOC: sz jmp mov mov mov mov EOCB polling_EOC a,ADRH adrh_buffer,a a,ADRL adrl_buffer,a : : jmp start_conversion ; start next A/D conversion ; poll the ADCR register EOCB bit to detect end of A/D conversion ; continue polling ; read conversion result high byte value from the ADRH register ; save result to user defined memory ; read conversion result low byte value from the ADRL register ; save result to user defined memory M in im u m START o n e in s tr u c tio n c y c le n e e d e d , M a x im u m te n in s tr u c tio n c y c le s a llo w e d EOCB PC R2~ PCR0 A /D s a m p lin g tim e tA D C S 000B 100B A /D tA DCS s a m p lin g tim e A /D tA DCS s a m p lin g tim e 000B 1 . P B p o rt s e tu p a s I/O s 2 . A /D c o n v e r te r is p o w e r e d o ff to r e d u c e p o w e r c o n s u m p tio n 100B 101B AC S2~ ACS0 000B P o w e r-o n R eset R e s e t A /D c o n v e rte r 1 : D e fin e P B c o n fig u r a tio n 2 : S e le c t a n a lo g c h a n n e l 010B S ta rt o f A /D c o n v e r s io n 000B S ta rt o f A /D c o n v e r s io n R e s e t A /D c o n v e rte r E n d o f A /D c o n v e r s io n 001B S ta rt o f A /D c o n v e r s io n R e s e t A /D c o n v e rte r E n d o f A /D c o n v e r s io n d o n 't c a r e E n d o f A /D c o n v e r s io n tA D C c o n v e r s io n tim e tA D C A /D c o n v e r s io n tim e N o te : A /D tA D tA CS A /D tA D C c o n v e r s io n tim e A /D DC c lo c k m u s t b e fS = 3 2 tA D = 7 6 tA D YS /2 , fS YS /8 o r fS YS /3 2 A/D Conversion Timing Comparator There is one Comparator in the device. The CMPEN bits is used as the enable or disable bits, if the CMPEN is cleared to 0, the Comparator is disabled, the PA1/CVINP, PA2/CVINN, PA3/COUT are all GPIO pins, if the CMPEN is set to 1, the Comparator is enabled, the PA1/CVINP, PA2/CVINN are Comparator input pins, PA3/COUT is a Comparator output pin. The CVINP, CVINN and COUT are pin-shared with PA1, PA2 and PA3. Once the Comparator function is used, the internal registers related to PA1, PA2 cannot be used, PA3 can be used as input only( if the COUTEN is 1), and the PA1, PA2 I/O function, PA3 output function and pull-high resistor are disabled automatically(if the COUTEN is 1). Once the Comparator function is used, the PA3 is the GPIO when the COUTEN is 0. Software instructions determine the Comparator function to be used. P A 1 /C V IN P P A 2 /C V IN N P A 3 /C O U T S1 S2 S3 C O F0~C O F3 CMPEN CMPOP In te rru p t CRS 0 0 1 1 COFM 0 1 0 1 S1 ON OFF ON ON S2 ON ON OFF ON S3 OFF ON OFF ON Comparator Block Diagram Rev. 1.00 28 January 11, 2007 HT45RM03 Bit No. 0~3 4 5 6 7 Label Function COF0~COF3 Comparator input offset voltage cancellation control bits CRS COFM CMPOP CMPEN Comparator input offset voltage cancellation reference selection bit 1/0: select CVINP/CVINN as the reference input Input offset voltage cancellation mode and comparator mode selection 1/0: input offset voltage cancellation mode/comparator mode Comparator output; positive logic. This bit is read only. Comparator enable/disable (1/0) CMPC Register (Comparator Control Register) CMPEN 0 1 1 COUTEN X 0 1 PA1, PA2, PA3 is GPIO PA1, PA2, PA3 PA1, PA2 is Comparator input pin and PA3 is GPIO. PA1, PA2 is Comparator input pin and PA3 is Comparator output pin. PA3 can read the Comparator output status. The Comparator enable/disable register, Comparator output pin enable/disable register and Comparator output flag are shown below. PA3/COUT selection COUTEN 0: PA3/COUT is as a GPIO pin 1: PA3/COUT is Comparator output, and the status of COUT can be read by reading the PA3 register. The Comparator can be used for stopping the PWM by PWWSP0 and PWMSP1 register, which are shown below. The stopping PWM is used to clear the PWMCTRL bit to 0. Stopping the PWMand PWM using hardware selection. The stopping PWM method is to clear PWMCTRL PWMSP0 bit to 0 by hardware. 00: PWM module output can be stop by software control only 01: PWM module output can be stop by COUT falling edge PWMSP1 10: PWM module output can be stop by INT1 interrupt 11: PWM module output can be stop by COUT falling edge or by INT1 interrupt OPA (Operation Amplifier) There is one OPA in the device. This OPA can be used for amplifier by user requirement. The OPAEN bits is used as the enable or disable bits, if the OPAEN is cleared to 0, the OPA is disabled and power off to save power consumption, the PB2/AN2/OPOUT, PB3/AN3/ OPVINN, PA0/OPVINP are all GPIO pins, if the OPAEN is set to 1, the OPA is enabled, the PB3/AN3/OPVINN and PA0/OPVINP are OPA inverting and non-inverting input pins, PB2/AN2/OPOUT is a OPA output pin, PB2, PB3, PA0 output and pull-high resistor are disabled. P A 0 /O P V IN P P B 3 /A N 3 /O P V IN N P B 2 /A N 2 /O P O U T S1 S2 S3 AO F0~AO F3 OPAEN OPAOP ARS 0 0 1 1 AOFM 0 1 0 1 S1 ON OFF ON ON S2 ON ON OFF ON S3 OFF ON OFF ON The OPA can be disabled or enabled by software control. The OPVINP, OPVINN and OPOUT are pin-shared with PA0, PB3/AN3 and PB2/AN2 respectively. Once the OPA function is used, the internal registers related to PA0, PB3 and PB2 cannot be used, and the I/O function and pull-high resistor are disabled automatically. Software instructions determine the OPA function to be used. Operational Amplifier Block Diagram Rev. 1.00 29 January 11, 2007 HT45RM03 Bit No. 0~3 4 5 6 7 Label Function AOF0~AOF3 Operational amplifier input offset voltage cancellation control bits ARS AOFM OPAOP OPAEN Operational amplifier input offset voltage cancellation reference selection bit 1/0: select OPP/OPN as the reference input Input offset voltage cancellation mode and operational amplifier mode selection 1/0: input offset voltage cancellation mode/operational amplifier mode Operational amplifier output; positive logic. This bit is read only. Operational amplifier enable/disable (1/0) OPAC Register (Operational Amplifier Control Register) OPAEN 0 1 PA0, PA3/AN3, PB2/AN2 PA0 is GPIO and PB2/AN2, PB3/AN3 is GPIO or analog ADC input by ADCR register. PA0, PB3/AN3 is OPA input pin and PB2/AN2 is OPA output pin. The PB2/AN2 and PB3/AN3 can be analog ADC input if the related ADC function is enabled. Miscellaneous Register There is one miscellaneous control registers for various functions. The Miscellaneous register is to enable/disable Comparator, enable/disable OPA, enable/disable Comparator COUT pin, enable/disable stopping PWM by hardware. Bit No. Label Function This bit is read only. Its is the PWM output level option. 0: PWM output will be defined as an active high 1: PWM output will be defined as an active low If the PWM function disable, this bit is invalid. 0 PWMLEV 1 This bit is read only. Its is the PWM output level option. 0: PWM output will be defined as an active high PWMCLEV 1: PWM output will be defined as an active low If the PWM function disable, this bit is invalid. PWMSP0 Stopping the PWM and PWM using hardware selection 00: PWM module output can be stop by software control only 01: PWM module output can be stop by COUT falling edge 10: PWM module output can be stop by INT1 interrupt 11: PWM module output can be stop by COUT falling edge or by INT1 interrupt 2 3 4 PWMSP1 PWMCTRL To active/inactive PWM and PWMC Complementary output (0=inactive; 1=active) PA3/COUT selection 0: PA3/COUT is as a GPIO pin 1: PA3/COUT is Comparator output, and the status of COUT can be read by reading the PA3 register. Comparator output flag. This bit is read only 0: Comparator output is low state 1: Comparator output is high state Unused bit, read as 0 MISC (1DH) Register 5 COUTEN 6 7 COUTR 3/4 Rev. 1.00 30 January 11, 2007 HT45RM03 Low Voltage Reset - LVR The microcontroller provides low voltage reset circuit in order to monitor the supply voltage of the device. If the supply voltage of the device is within the range 0.9V~VLVR, such as changing a battery, the LVR will automatically reset the device internally. The LVR includes the following specifications: * The low voltage (0.9V~VLVR) has to remain in their original state to exceed tLVR. If the low voltage state does not exceed tLVR, the LVR will ignore it and do not perform a reset function. * The LVR uses the OR function with the external RES signal to perform chip reset. The relationship between VDD and VLVR is shown below. VDD 5 .5 V V OPR 5 .5 V VDD 5 .5 V V OPR 5 .5 V VDD 5 .5 V V OPR 5 .5 V V V 2 .1 V 2 .2 V LVR V LVR LVR 3 .1 5 V 4 .2 V 2 .2 V 2 .2 V 0 .9 V 0 .9 V 0 .9 V Note: VOPR is the voltage range for proper chip operation at 4MHz system clock. V 5 .5 V DD V LVR LVR D e te c t V o lta g e 0 .9 V 0V R e s e t S ig n a l R eset *1 N o r m a l O p e r a tio n *2 R eset Low Voltage Reset Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: Since low voltage state has to be maintained in its original state for over tLVR, therefore after tLVR delay, the device enters the reset mode. Rev. 1.00 31 January 11, 2007 HT45RM03 Options No. 1 2 Options OSC type selection. This option is to decide if an RC or crystal oscillator is chosen as system clock. WDT source selection. There are three types of selection: on-chip RC oscillator, instruction clock or disable the WDT. CLRWDT times selection. This option defines how to clear the WDT by instruction. One time means that the CLR WDT instruction can clear the WDT. Two times means only if both of the CLR WDT1 and CLR WDT2 instructions have been executed, then WDT can be cleared. Wake-up selection. This option defines the wake-up function activity. External I/O pins (PA only) all have the capability to wake-up the chip from a HALT. Pull-high selection. This option is to decide whether a pull-high resistance is visible or not in the input mode of the I/O ports. PA0~PA7, PB0~PB7, can be independently selected. PFD selection: PD0: level output or PFD output Low voltage reset selection: Enable or disable LVR function, and LVR voltage selection. PWM mode selection: 10 (9+1), (8+2) or (7+3) mode INT0A, INT0B, INT0C and INT1 trigger edge: disable; high to low; low to high or low to high or high to low. PWM output level selection; PWMLEV. This option is to determine the PWM output level. Active Low or Active High selection. Disable this bit to 0, the PWM output will be defined as an active high output, Enable this bit to 1, the PWM output will be defined as an active low output. If the PWM function disable, this bit is invalid. PWM Complementary output level selection; PWMCLEV. This option is to determine the PWM Complementary output level. Active low or active high selection. Disable this bit to 0, the PWM Complementary output will be defined as an active high output, Enable this bit to 1, the PWM Complementary output will be defined as an active low output. If the PWM Complementary function disable, this bit is invalid. 3 4 5 6 7 8 9 10 11 Rev. 1.00 32 January 11, 2007 HT45RM03 Application Circuits Application Circuits 1 V DD 0 .0 1 m F * 100kW 0 .1 m F 10kW VDD RES M OSFET & D r iv e r BLDC VSS P A 4 /IN T 0 A P A 5 /IN T 0 B P A 6 /IN T 0 C P A 7 /IN T 1 P A 2 /C V IN N P A 1 /C V IN P P A 3 /C O U T P B 7 /A N 7 /T M R 0 /T M R 1 P B 0 /A N 0 ~ P B 1 /A N 1 P B 4 /A N 4 ~ P B 6 /A N 6 P B 2 /A N 2 /O P P B 3 /A N 3 /O P A 0 /O PD0 HT45RM 03 OU P IN P IN /P F D T N P C2 R1 R PC 0~PC 5 0 .1 m F * OSC C ir c u it S e e R ig h t S id e OSC1 OSC2 H A L L S e n s o r In p u t V DD 470pF OSC OSC1 fS YS R C S y s te m O s c illa to r 24kW OSC2 OSC1 C ry s ta l S y s te m F o r th e v a lu e s , s e e ta b le b e lo w O s c illa to r C1 OSC2 OSC C ir c u it The following table shows the C1, C2 and R1 values corresponding to the different crystal values. (For reference only) Crystal or Resonator 8MHz Crystal 8MHz Resonator 4MHz Crystal 4MHz Resonator 3.58MHz Crystal 3.58MHz Resonator 2MHz Crystal 2MHz Resonator 1MHz Crystal 480kHz Resonator 455kHz Resonator 429kHz Resonator 400kHz Resonator C1, C2 0pF 10pF 0pF 10pF 0pF 25pF 25pF 25pF 35pF 300pF, 100pF 300pF 300pF 300pF R1 5.3kW 6.3kW 13kW 12kW 15kW 10kW 10kW 12kW 15kW 9.1kW 10kW 10kW 10kW The function of the resistor R1 is to ensure that the oscillator will switch off should low voltage conditions occur. Such a low voltage, as mentioned here, is one which is less than the lowest value of the MCU operating voltage. Note however that if the LVR is enabled then R1 can be removed. Note: The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RES high. * Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference. Rev. 1.00 33 January 11, 2007 HT45RM03 Application Circuits 2 1 V DD R4 3 4 5 O v e r C u rre n t 6 7 R2 R3 R5 C u rre n tA N B A T V o lA N SpeedAN PW M0 PW M0 PW M1 9 10 11 12 13 14 8 R1 2 P B 5 /A N 5 P B 4 /A N 4 P A 3 /C O U T P A 2 /C V IN N P A 1 /C V IN P P A 0 /O P V IN P P B 3 /A N 3 /O P V IN N P B 2 /A N 2 /O P O U T P B 1 /A N 1 P B 0 /A N 0 VSS P C 0 /P W M 0 P C 1 /P W M 0 P C 2 /P W M 1 H T45R M 03 P B 6 /A N 6 P B 7 /A N 7 /T M R 0 /T M R 1 P A 4 /IN T 0 A P A 5 /IN T 0 B P A 6 /IN T 0 C P A 7 /IN T 1 OSC2 OSC1 VDD RES P D 0 /P F D P C 5 /P W M 2 P C 4 /P W M 2 P C 3 /P W M 1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PW M2 PW M2 PW M1 C3 R7 VDD C1 R6 C2 B r a k e S ig n a l S e n s o r_ C S e n s o r_ B S e n s o r_ A RunUp V DD V M D1 1 2 VSS VDD 4 5 6 7 8 9 10 11 12 PW M0 PW M0 PW M1 PW M1 PW M2 PW M2 R8 R9 R 10 R 11 R 12 R 13 3 VM NC VSS VDD ATL ABL BTL BBL CTL CBL NC VSS H T45B 0C U bat AT R14 R15 P hase A AB R16 R17 O v e r_ c u rre n t CN1 C10 Q2 P hase B BB R20 R21 R22 R23 V 1 2 R29 R30 B r a k e S ig n a l SpeedAN 4 H4 5 H3 C16 C17 C18 C14 C15 R31 4 3 VSS VDD R32 R33 R34 R35 R36 R37 S e n s o r_ C S e n s o r_ B S e n s o r_ A DD VDAT AT VSAT AB VDBT BT VSBT BB VDCT CT VSCT CB 24 23 22 21 20 19 18 17 16 15 14 13 CB CT BB BT AB AT C4 + C5 P hase A + D2 C6 C7 P hase B + D3 C8 C9 P hase C Q1 BT R18 R19 CN2 C11 CT R24 R25 CN3 R26 R27 C12 P hase C CB 1 2 3 H2 VSS VDD RunUp R28 C13 3 2 1 VSS VDD U bat Ubat C19 C20 +48V VSS CN4 CN5 CN6 R38 C21 +48V R39 R40 +48V R41 B A T V o lA N C22 R42 C23 LM 317 +15V C24 VM 78L05 C25 2 V +5V C26 DD R43 R44 C27 Rev. 1.00 34 January 11, 2007 HT45RM03 Instruction Set Summary Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to data memory with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry and result in data memory Decimal adjust ACC for addition with result in data memory 1 1(1) 1 1 1(1) 1 1 1(1) 1 1(1) 1(1) Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV C Description Instruction Cycle Flag Affected Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC 1 1 1 1(1) 1(1) 1(1) 1 1 1 1(1) 1 Z Z Z Z Z Z Z Z Z Z Z Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Clear bit of data memory Set bit of data memory 1(1) 1(1) None None Move data memory to ACC Move ACC to data memory Move immediate data to ACC 1 1(1) 1 None None None Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry 1 1(1) 1 1(1) 1 1(1) 1 1(1) None None C C None None C C Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory 1 1(1) 1 1(1) Z Z Z Z Rev. 1.00 35 January 11, 2007 HT45RM03 Mnemonic Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: No operation Clear data memory Set data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter power down mode 1 1(1) 1(1) 1 1 1 1(1) 1 1 None None None TO,PDF TO(4),PDF(4) TO(4),PDF(4) None None TO,PDF Read ROM code (current page) to data memory and TBLH Read ROM code (last page) to data memory and TBLH 2(1) 2(1) None None Jump unconditionally Skip if data memory is zero Skip if data memory is zero with data movement to ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result in ACC Skip if decrement data memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) 2 2 2 2 None None None None None None None None None None None None None Description Instruction Cycle Flag Affected x: Immediate data m: Data memory address A: Accumulator i: 0~7 number of bits addr: Program memory address O: Flag is affected -: Flag is not affected (1) : If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). : If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged. : and (2) : The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. (2) (3) (1) (4) Rev. 1.00 36 January 11, 2007 HT45RM03 Instruction Definition ADC A,[m] Description Operation Affected flag(s) TO 3/4 ADCM A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,x Description Operation Affected flag(s) TO 3/4 ADDM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Add data memory and carry to the accumulator The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. ACC ACC+[m]+C Add the accumulator and carry to data memory The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. [m] ACC+[m]+C Add data memory to the accumulator The contents of the specified data memory and the accumulator are added. The result is stored in the accumulator. ACC ACC+[m] Add immediate data to the accumulator The contents of the accumulator and the specified data are added, leaving the result in the accumulator. ACC ACC+x Add the accumulator to the data memory The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. [m] ACC+[m] Rev. 1.00 37 January 11, 2007 HT45RM03 AND A,[m] Description Operation Affected flag(s) TO 3/4 AND A,x Description Operation Affected flag(s) TO 3/4 ANDM A,[m] Description Operation Affected flag(s) TO 3/4 CALL addr Description PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical AND accumulator with data memory Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND [m] Logical AND immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND x Logical AND data memory with the accumulator Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory. [m] ACC AND [m] Subroutine call The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this address. Stack Program Counter+1 Program Counter addr TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) CLR [m] Description Operation Affected flag(s) Clear data memory The contents of the specified data memory are cleared to 0. [m] 00H TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Rev. 1.00 38 January 11, 2007 HT45RM03 CLR [m].i Description Operation Affected flag(s) TO 3/4 CLR WDT Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Clear bit of data memory The bit i of the specified data memory is cleared to 0. [m].i 0 Clear Watchdog Timer The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are cleared. WDT 00H PDF and TO 0 TO 0 PDF 0 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) CLR WDT1 Description Preclear Watchdog Timer Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0* TO 0* PDF 0* OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) CLR WDT2 Description Preclear Watchdog Timer Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0* TO 0* PDF 0* OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) CPL [m] Description Operation Affected flag(s) Complement data memory Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. [m] [m] TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Rev. 1.00 39 January 11, 2007 HT45RM03 CPLA [m] Description Complement data memory and place result in the accumulator Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged. ACC [m] TO 3/4 DAA [m] Description PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Operation Affected flag(s) Decimal-Adjust accumulator for addition The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored in the data memory and only the carry flag (C) may be affected. If ACC.3~ACC.0 >9 or AC=1 then [m].3~[m].0 (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0 (ACC.3~ACC.0), AC1=0 and If ACC.7~ACC.4+AC1 >9 or C=1 then [m].7~[m].4 ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ACC.7~ACC.4+AC1,C=C TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O Operation Affected flag(s) DEC [m] Description Operation Affected flag(s) Decrement data memory Data in the specified data memory is decremented by 1. [m] [m]-1 TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 DECA [m] Description Operation Affected flag(s) Decrement data memory and place result in the accumulator Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]-1 TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Rev. 1.00 40 January 11, 2007 HT45RM03 HALT Description Enter power down mode This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PDF) is set and the WDT time-out bit (TO) is cleared. Program Counter Program Counter+1 PDF 1 TO 0 TO 0 INC [m] Description Operation Affected flag(s) TO 3/4 INCA [m] Description Operation Affected flag(s) TO 3/4 JMP addr Description Operation Affected flag(s) TO 3/4 MOV A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Directly jump The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. Program Counter addr PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 1 OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) Increment data memory Data in the specified data memory is incremented by 1 [m] [m]+1 Increment data memory and place result in the accumulator Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]+1 Move data memory to the accumulator The contents of the specified data memory are copied to the accumulator. ACC [m] Rev. 1.00 41 January 11, 2007 HT45RM03 MOV A,x Description Operation Affected flag(s) TO 3/4 MOV [m],A Description Operation Affected flag(s) TO 3/4 NOP Description Operation Affected flag(s) TO 3/4 OR A,[m] Description Operation Affected flag(s) TO 3/4 OR A,x Description Operation Affected flag(s) TO 3/4 ORM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 No operation No operation is performed. Execution continues with the next instruction. Program Counter Program Counter+1 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move immediate data to the accumulator The 8-bit data specified by the code is loaded into the accumulator. ACC x Move the accumulator to data memory The contents of the accumulator are copied to the specified data memory (one of the data memories). [m] ACC Logical OR accumulator with data memory Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR [m] Logical OR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR x Logical OR data memory with the accumulator Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. [m] ACC OR [m] Rev. 1.00 42 January 11, 2007 HT45RM03 RET Description Operation Affected flag(s) TO 3/4 RET A,x Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Return from subroutine The program counter is restored from the stack. This is a 2-cycle instruction. Program Counter Stack Return and place immediate data in the accumulator The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. Program Counter Stack ACC x TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) RETI Description Operation Return from interrupt The program counter is restored from the stack, and interrupts are enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit. Program Counter Stack EMI 1 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) RL [m] Description Operation Rotate data memory left The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) RLA [m] Description Operation Rotate data memory left and place result in the accumulator Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) Rev. 1.00 43 January 11, 2007 HT45RM03 RLC [m] Description Operation Rotate data memory left through carry The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 C C [m].7 TO 3/4 RLCA [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O Affected flag(s) Rotate left through carry and place result in the accumulator Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 C C [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O Operation Affected flag(s) RR [m] Description Operation Rotate data memory right The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) RRA [m] Description Operation Rotate right and place result in the accumulator Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) RRC [m] Description Operation Rotate data memory right through carry The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 C C [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O Affected flag(s) Rev. 1.00 44 January 11, 2007 HT45RM03 RRCA [m] Description Rotate right through carry and place result in the accumulator Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged. ACC.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 C C [m].0 TO 3/4 SBC A,[m] Description Operation Affected flag(s) TO 3/4 SBCM A,[m] Description Operation Affected flag(s) TO 3/4 SDZ [m] Description PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O Operation Affected flag(s) Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator. ACC ACC+[m]+C Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. [m] ACC+[m]+C Skip if decrement data memory is 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, [m] ([m]-1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) SDZA [m] Description Decrement data memory and place result in ACC, skip if 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, ACC ([m]-1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) Rev. 1.00 45 January 11, 2007 HT45RM03 SET [m] Description Operation Affected flag(s) TO 3/4 SET [m]. i Description Operation Affected flag(s) TO 3/4 SIZ [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Set data memory Each bit of the specified data memory is set to 1. [m] FFH Set bit of data memory Bit i of the specified data memory is set to 1. [m].i 1 Skip if increment data memory is 0 The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, [m] ([m]+1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) SIZA [m] Description Increment data memory and place result in ACC, skip if 0 The contents of the specified data memory are incremented by 1. If the result is 0, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, ACC ([m]+1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) SNZ [m].i Description Skip if bit i of the data memory is not 0 If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i0 Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Rev. 1.00 46 January 11, 2007 HT45RM03 SUB A,[m] Description Operation Affected flag(s) TO 3/4 SUBM A,[m] Description Operation Affected flag(s) TO 3/4 SUB A,x Description Operation Affected flag(s) TO 3/4 SWAP [m] Description Operation Affected flag(s) TO 3/4 SWAPA [m] Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+[m]+1 Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. [m] ACC+[m]+1 Subtract immediate data from the accumulator The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+x+1 Swap nibbles within the data memory The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged. [m].3~[m].0 [m].7~[m].4 Swap data memory and place result in the accumulator The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) Rev. 1.00 47 January 11, 2007 HT45RM03 SZ [m] Description Skip if data memory is 0 If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0 Operation Affected flag(s) TO 3/4 SZA [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move data memory to ACC, skip if 0 The contents of the specified data memory are copied to the accumulator. If the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0 Operation Affected flag(s) TO 3/4 SZ [m].i Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Skip if bit i of the data memory is 0 If bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i=0 Operation Affected flag(s) TO 3/4 TABRDC [m] Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move the ROM code (current page) to TBLH and data memory The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) TABRDL [m] Description Operation Move the ROM code (last page) to TBLH and data memory The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) Rev. 1.00 48 January 11, 2007 HT45RM03 XOR A,[m] Description Operation Affected flag(s) TO 3/4 XORM A,[m] Description Operation Affected flag(s) TO 3/4 XOR A,x Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical XOR accumulator with data memory Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator. ACC ACC XOR [m] Logical XOR data memory with the accumulator Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected. [m] ACC XOR [m] Logical XOR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected. ACC ACC XOR x Rev. 1.00 49 January 11, 2007 HT45RM03 Package Information 28-pin SKDIP (300mil) Outline Dimensions A 28 B 1 15 14 H C D E F G a I Symbol A B C D E F G H I a Dimensions in mil Min. 1375 278 125 125 16 50 3/4 295 330 0 Nom. 3/4 3/4 3/4 3/4 3/4 3/4 100 3/4 3/4 3/4 Max. 1395 298 135 145 20 70 3/4 315 375 15 Rev. 1.00 50 January 11, 2007 HT45RM03 28-pin SOP (300mil) Outline Dimensions 28 A 15 B 1 14 C C' G H D E F a Symbol A B C C D E F G H a Dimensions in mil Min. 394 290 14 697 92 3/4 4 32 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 50 3/4 3/4 3/4 3/4 Max. 419 300 20 713 104 3/4 3/4 38 12 10 Rev. 1.00 51 January 11, 2007 HT45RM03 Product Tape and Reel Specifications Reel Dimensions T2 D A B C T1 SOP 28W (300mil) Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 3301.0 621.5 13.0+0.5 -0.2 2.00.5 24.8+0.3 -0.2 30.20.2 Rev. 1.00 52 January 11, 2007 HT45RM03 Carrier Tape Dimensions D E F W C P0 P1 t B0 D1 P K0 A0 SOP 28W Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 24.00.3 12.00.1 1.750.1 11.50.1 1.5+0.1 1.5+0.25 4.00.1 2.00.1 10.850.1 18.340.1 2.970.1 0.350.01 21.3 Rev. 1.00 53 January 11, 2007 HT45RM03 Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 86-21-6485-5560 Fax: 86-21-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9533 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 Fax: 86-10-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 86-28-6653-6590 Fax: 86-28-6653-6591 Holmate Semiconductor, Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holmate.com Copyright O 2007 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 54 January 11, 2007 |
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